ERET -> xRET; new memory map

For now, we no longer build hex files, because the programs don't
start at address 0.  This decision will likely be revisited.

22 files changed, 152 insertions, 1201 deletions

diff --git a/benchmarks/Makefile b/benchmarks/Makefile
index 1145fed..8cc1e35 100644
--- a/benchmarks/Makefile
+++ b/benchmarks/Makefile
@@ -48,10 +48,10 @@ HOST_COMP = gcc $(HOST_OPTS)
 
 RISCV_PREFIX ?= riscv64-unknown-elf-
 RISCV_GCC ?= $(RISCV_PREFIX)gcc
-RISCV_GCC_OPTS ?= -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf
+RISCV_GCC_OPTS ?= -fpie -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf
 RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs)
 RISCV_LINK_MT ?= $(RISCV_GCC) -T $(src_dir)/common/test-mt.ld
-RISCV_LINK_OPTS ?= -nostdlib -nostartfiles -ffast-math -lc -lgcc
+RISCV_LINK_OPTS ?= -nostdlib -nostartfiles -ffast-math -lgcc
 RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data
 RISCV_SIM ?= spike
 
@@ -68,15 +68,11 @@ include $(patsubst %, $(src_dir)/%/bmark.mk, $(bmarks))
 
 bmarks_riscv_bin  = $(addsuffix .riscv,  $(bmarks))
 bmarks_riscv_dump = $(addsuffix .riscv.dump, $(bmarks))
-bmarks_riscv_hex = $(addsuffix .riscv.hex, $(bmarks))
 bmarks_riscv_out  = $(addsuffix .riscv.out,  $(bmarks))
 
 bmarks_defs   = -DPREALLOCATE=1 -DHOST_DEBUG=0
 bmarks_cycles = 80000
 
-%.hex: %
-	elf2hex 16 32768 $< > $@
-
 $(bmarks_riscv_dump): %.riscv.dump: %.riscv
 	$(RISCV_OBJDUMP) $< > $@
 
@@ -91,7 +87,7 @@ $(bmarks_riscv_out): %.riscv.out: %.riscv
 	$(RISCV_GCC) $(RISCV_GCC_OPTS) $(bmarks_defs) -D__ASSEMBLY__=1 \
 	             -c $(incs) $< -o $@
 
-riscv: $(bmarks_riscv_dump) $(bmarks_riscv_hex)
+riscv: $(bmarks_riscv_dump)
 run-riscv: $(bmarks_riscv_out)
 	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
 	       $(bmarks_riscv_out); echo;
diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index 919461b..634b864 100644
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -15,15 +15,9 @@
   .text
   .globl _start
 _start:
-  j handle_reset
+  la t0, trap_entry
+  csrw mtvec, t0
 
-nmi_vector:
-  j nmi_vector
-
-trap_vector:
-  j trap_entry
-
-handle_reset:
   li  x1, 0
   li  x2, 0
   li  x3, 0
@@ -216,7 +210,7 @@ trap_entry:
   LREG x31, 31*REGBYTES(sp)
 
   addi sp, sp, 272
-  eret
+  mret
 
 .section ".tdata.begin"
 .globl _tdata_begin
diff --git a/benchmarks/common/syscalls.c b/benchmarks/common/syscalls.c
index 87fd358..4620631 100644
--- a/benchmarks/common/syscalls.c
+++ b/benchmarks/common/syscalls.c
@@ -406,3 +406,95 @@ int sprintf(char* str, const char* fmt, ...)
   va_end(ap);
   return str - str0;
 }
+
+void* memcpy(void* dest, const void* src, size_t len)
+{
+  if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) {
+    const uintptr_t* s = src;
+    uintptr_t *d = dest;
+    while (d < (uintptr_t*)(dest + len))
+      *d++ = *s++;
+  } else {
+    const char* s = src;
+    char *d = dest;
+    while (d < (char*)(dest + len))
+      *d++ = *s++;
+  }
+  return dest;
+}
+
+void* memset(void* dest, int byte, size_t len)
+{
+  if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) {
+    uintptr_t word = byte & 0xFF;
+    word |= word << 8;
+    word |= word << 16;
+    word |= word << 16 << 16;
+
+    uintptr_t *d = dest;
+    while (d < (uintptr_t*)(dest + len))
+      *d++ = word;
+  } else {
+    char *d = dest;
+    while (d < (char*)(dest + len))
+      *d++ = byte;
+  }
+  return dest;
+}
+
+size_t strlen(const char *s)
+{
+  const char *p = s;
+  while (*p)
+    p++;
+  return p - s;
+}
+
+size_t strnlen(const char *s, size_t n)
+{
+  const char *p = s;
+  while (n-- && *p)
+    p++;
+  return p - s;
+}
+
+int strcmp(const char* s1, const char* s2)
+{
+  unsigned char c1, c2;
+
+  do {
+    c1 = *s1++;
+    c2 = *s2++;
+  } while (c1 != 0 && c1 == c2);
+
+  return c1 - c2;
+}
+
+char* strcpy(char* dest, const char* src)
+{
+  char* d = dest;
+  while ((*d++ = *src++))
+    ;
+  return dest;
+}
+
+long atol(const char* str)
+{
+  long res = 0;
+  int sign = 0;
+
+  while (*str == ' ')
+    str++;
+
+  if (*str == '-' || *str == '+') {
+    sign = *str == '-';
+    str++;
+  }
+
+  while (*str) {
+    res *= 10;
+    res += *str++ - '0';
+  }
+
+  return sign ? -res : res;
+}
diff --git a/benchmarks/common/test.ld b/benchmarks/common/test.ld
index 00eb4a2..7ee56b6 100644
--- a/benchmarks/common/test.ld
+++ b/benchmarks/common/test.ld
@@ -21,7 +21,7 @@ SECTIONS
 {
 
   /* text: test code section */
-  . = 0x0;
+  . = 0x80000000;
   .text : 
   {
     crt.o(.text)
diff --git a/env b/env
-Subproject 0fc840489c21530a8bfdaecac1131fcd20bdaea
+Subproject 3d45ca302dbf5ac22cfac8fb025c05c735c35e2
diff --git a/isa/Makefile b/isa/Makefile
index 4ff1bd3..636cbbe 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -31,9 +31,6 @@ vpath %.S $(src_dir)
 #------------------------------------------------------------
 # Build assembly tests
 
-%.hex: %
-	(elf2hex 16 8192 $< 2> /dev/null || elf2hex 16 16384 $<) > $@
-
 %.dump: %
 	$(RISCV_OBJDUMP) $< > $@
 
@@ -49,22 +46,13 @@ $$($(1)_p_tests): $(1)-p-%: $(1)/%.S
 	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $$@
 $(1)_tests += $$($(1)_p_tests)
 
-$$($(1)_pt_tests): $(1)-pt-%: $(1)/%.S
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/pt -I$(src_dir)/macros/scalar -T$(src_dir)/../env/pt/link.ld $$< -o $$@
-$(1)_tests += $$($(1)_pt_tests)
-
-$$($(1)_pm_tests): $(1)-pm-%: $(1)/%.S
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/pm -I$(src_dir)/macros/scalar -T$(src_dir)/../env/pm/link.ld $$< -o $$@
-$(1)_tests += $$($(1)_pm_tests)
-
 $$($(1)_v_tests): $(1)-v-%: $(1)/%.S
 	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -lc -o $$@
 $(1)_tests += $$($(1)_v_tests)
 
 $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
-$(1)_tests_hex = $$(addsuffix .hex, $$($(1)_tests))
 
-$(1): $$($(1)_tests_dump) $$($(1)_tests_hex)
+$(1): $$($(1)_tests_dump)
 
 .PHONY: $(1)
 
@@ -96,7 +84,7 @@ junk += $(tests) $(tests_dump) $(tests_hex) $(tests_out) $(tests32_out)
 #------------------------------------------------------------
 # Default
 
-all: $(tests_dump) $(tests_hex)
+all: $(tests_dump)
 
 #------------------------------------------------------------
 # Clean up
diff --git a/isa/macros/vector/test_macros.h b/isa/macros/vector/test_macros.h
index a97ffe7..7ee9262 100644
--- a/isa/macros/vector/test_macros.h
+++ b/isa/macros/vector/test_macros.h
@@ -20,8 +20,8 @@ test_ ## testnum: \
   vsetcfg nxreg,nfreg; \
   li a3,2048; \
   vsetvl a3,a3; \
-  lui a0,%hi(vtcode ## testnum ); \
-  vf %lo(vtcode ## testnum )(a0); \
+1:auipc a0,%pcrel_hi(vtcode ## testnum); \
+  vf %pcrel_lo(1b)(a0); \
   la a4,dst; \
   vsd v ## testreg, a4; \
   fence; \
@@ -233,8 +233,8 @@ test_ ## testnum: \
   addi a5,a5,4; \
   vflstw vf2, a5, x0; \
   addi a5,a5,4; \
-  lui a0,%hi(vtcode ## testnum ); \
-  vf %lo(vtcode ## testnum )(a0); \
+1:auipc a0,%pcrel_hi(vtcode ## testnum); \
+  vf %pcrel_lo(1b)(a0); \
   la a4,dst; \
   vsw vx1, a4; \
   fence; \
@@ -273,8 +273,8 @@ test_ ## testnum: \
   addi a5,a5,8; \
   vflstd vf2, a5, x0; \
   addi a5,a5,8; \
-  lui a0,%hi(vtcode ## testnum ); \
-  vf %lo(vtcode ## testnum )(a0); \
+1:auipc a0,%pcrel_hi(vtcode ## testnum); \
+  vf %pcrel_lo(1b)(a0); \
   la a4,dst; \
   vsd vx1, a4; \
   fence; \
@@ -346,8 +346,8 @@ test_ ## testnum: \
   vsetcfg 2,1; \
   li a3,2048; \
   vsetvl a3,a3; \
-  lui a0,%hi(vtcode ## testnum ); \
-  vf %lo(vtcode ## testnum )(a0); \
+1:auipc a0,%pcrel_hi(vtcode ## testnum); \
+  vf %pcrel_lo(1b)(a0); \
   la a4,dst; \
   vsw vx1, a4; \
   fence; \
@@ -379,8 +379,8 @@ test_ ## testnum: \
   vsetcfg 2,1; \
   li a3,2048; \
   vsetvl a3,a3; \
-  lui a0,%hi(vtcode ## testnum ); \
-  vf %lo(vtcode ## testnum )(a0); \
+1:auipc a0,%pcrel_hi(vtcode ## testnum); \
+  vf %pcrel_lo(1b)(a0); \
   la a4,dst; \
   vsd vx1, a4; \
   fence; \
@@ -529,8 +529,8 @@ test_ ## testnum: \
   vsetcfg nxreg,nfreg; \
   li a3,2048; \
   vsetvl a3,a3; \
-  lui a0,%hi(vtcode ## testnum ); \
-  vf %lo(vtcode ## testnum )(a0); \
+1:auipc a0,%pcrel_hi(vtcode ## testnum); \
+  vf %pcrel_lo(1b)(a0); \
   la a4,dst; \
   fence; \
   li a1,correctval; \
diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag
index 66a0e39..9aeb12d 100644
--- a/isa/rv32mi/Makefrag
+++ b/isa/rv32mi/Makefrag
@@ -12,13 +12,11 @@ rv32mi_sc_tests = \
 	scall \
 	sbreak \
 	shamt \
-	timer \
 	wfi \
 
 rv32mi_mc_tests = \
 	ipi \
 
 rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests))
-rv32mi_pm_tests = $(addprefix rv32mi-pm-, $(rv32mi_mc_tests))
 
-spike32_tests += $(rv32mi_p_tests) $(rv32mi_pm_tests)
+spike32_tests += $(rv32mi_p_tests)
diff --git a/isa/rv32mi/timer.S b/isa/rv32mi/timer.S
deleted file mode 100644
index 307876c..0000000
--- a/isa/rv32mi/timer.S
+++ /dev/null
@@ -1,7 +0,0 @@
-# See LICENSE for license details.
-
-#include "riscv_test.h"
-#undef RVTEST_RV64M
-#define RVTEST_RV64M RVTEST_RV32M
-
-#include "../rv64mi/timer.S"
diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag
index 95943b7..8124c02 100644
--- a/isa/rv32ui/Makefrag
+++ b/isa/rv32ui/Makefrag
@@ -29,8 +29,6 @@ rv32ui_mc_tests = \
 	lrsc
 
 rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
-rv32ui_pt_tests = $(addprefix rv32ui-pt-, $(rv32ui_sc_tests))
-rv32ui_pm_tests = $(addprefix rv32ui-pm-, $(rv32ui_mc_tests))
 rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests))
 
-spike32_tests += $(rv32ui_p_tests) $(rv32ui_pt_tests) $(rv32ui_pm_tests) $(rv32ui_v_tests)
+spike32_tests += $(rv32ui_p_tests) $(rv32ui_v_tests)
diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag
index b8b1da0..ed973db 100644
--- a/isa/rv64mi/Makefrag
+++ b/isa/rv64mi/Makefrag
@@ -12,12 +12,10 @@ rv64mi_sc_tests = \
 	scall \
 	wfi \
 	sbreak \
-	timer \
 
 rv64mi_mc_tests = \
 	ipi \
 
 rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests))
-rv64mi_pm_tests = $(addprefix rv64mi-pm-, $(rv64mi_mc_tests))
 
-spike_tests += $(rv64mi_p_tests) $(rv64mi_pm_tests)
+spike_tests += $(rv64mi_p_tests)
diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
index 73d6c6c..5228129 100644
--- a/isa/rv64mi/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -16,13 +16,17 @@ RVTEST_CODE_BEGIN
   # Turn on VM with superpage identity mapping
   la a1, page_table_1
   srl a1, a1, RISCV_PGSHIFT
+  la a2, page_table_2
+  srl a2, a2, RISCV_PGSHIFT
   csrw sptbr, a1
   sfence.vm
   li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
   csrs mstatus, a1
-  la a1, 1f
+  la a1, 1f - DRAM_BASE
   csrw mepc, a1
-  eret
+  la a1, stvec_handler - DRAM_BASE
+  csrw stvec, a1
+  mret
 1:
 
   # Try a faulting store to make sure dirty bit is not set
@@ -32,9 +36,7 @@ RVTEST_CODE_BEGIN
 
   # Load new page table
   li TESTNUM, 3
-  la t0, page_table_2
-  srl t0, t0, RISCV_PGSHIFT
-  csrw sptbr, t0
+  csrw sptbr, a2
   sfence.vm
 
   # Try a non-faulting store to make sure dirty bit is set
@@ -76,9 +78,9 @@ die:
 
 .data
 .align 12
-page_table_1: .dword PTE_V | PTE_TYPE_URX_SRX
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URX_SRX
 dummy: .dword 0
 .align 12
-page_table_2: .dword PTE_V | PTE_TYPE_URWX_SRWX
+page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URWX_SRWX
 
 RVTEST_CODE_END
diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
index ecb3088..30c22b2 100644
--- a/isa/rv64mi/illegal.S
+++ b/isa/rv64mi/illegal.S
@@ -28,7 +28,7 @@ mtvec_handler:
   csrr t0, mepc
   addi t0, t0, 8
   csrw mepc, t0
-  sret
+  mret
 
 RVTEST_CODE_END
 
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index aa5dd85..ed177f5 100644
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -72,7 +72,7 @@ mtvec_handler:
   csrr t0, mepc
   addi t0, t0, 8
   csrw mepc, t0
-  sret
+  mret
 
 RVTEST_CODE_END
 
diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index 4bb0445..f704827 100644
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -23,13 +23,15 @@ RVTEST_CODE_BEGIN
   # Check that mhartid reports 0
   TEST_CASE(3, a0, 0x0, csrr a0, mhartid)
 
-  # Check that reading mimpid, marchid, and mvendorid doesn't cause exceptions
+  # Check that reading the following CSRs doesn't cause an exception
   csrr a0, mimpid
   csrr a0, marchid
   csrr a0, mvendorid
 
-  # Check that mtvec reports DEFAULT_MTVEC
-  TEST_CASE(5, a0, DEFAULT_MTVEC, csrr a0, mtvec)
+  # Check that writing hte following CSRs doesn't cause an exception
+  li t0, 0
+  csrs mtvec, t0
+  csrs mepc, t0
 
   TEST_PASSFAIL
 
diff --git a/isa/rv64mi/timer.S b/isa/rv64mi/timer.S
deleted file mode 100644
index 4697793..0000000
--- a/isa/rv64mi/timer.S
+++ /dev/null
@@ -1,1103 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# timer.S
-#-----------------------------------------------------------------------------
-#
-# Test timer interrupts.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64M
-RVTEST_CODE_BEGIN
-
-#define DELTA_T 5
-
-  li s8, 0         # number of taken timer interrupts
-  li s9, 10        # how many interrupts to run for
-
-  .align 4
-  csrr a0, mtime
-  add a0, a0, DELTA_T
-  csrw mtimecmp, a0
-  li a0, MIP_MTIP
-  csrs mie, a0
-  csrs mstatus, MSTATUS_MIE
-
-  # advance an LFSR until the timer has fired enough times
-  li s0, 1023
-  li s4, 0
-1:srl s2,s0,3
-  xor s2,s2,s0
-  and s2,s2,1
-  srl s0,s0,1
-  sll s2,s2,9
-  or  s0,s2,s0
-  and s0, s0, 0x3FF
-  add s4, s4, 1
-  bltu s8, s9, 1b
-
-  # compute iteration count % 1023 without using REMU
-  li s1, 1023
-  bltu s4, s1, 2f
-1:sub s4, s4, s1
-  bgeu s4, s1, 1b
-2:
-
-  # make sure the LFSR was computed correctly
-  la s1, lfsr
-  sll s4, s4, 2
-  add s1, s1, s4
-  lw s1, (s1)
-  li TESTNUM, 2
-  bne s0, s1, fail
-
-  RVTEST_PASS
-
-  TEST_PASSFAIL
-
-mtvec_handler:
-  li TESTNUM, 3
-  csrr t0, mcause
-  bgez t0, fail
-
-  sll t0, t0, 1
-  addi t0, t0, -2*IRQ_M_TIMER
-  bnez t0, fail
-
-  csrr t0, mtime
-  addi t0, t0, DELTA_T
-  csrw mtimecmp, t0
-
-  add s8, s8, 1
-  eret
-
-.data
-lfsr:
-.word 1023
-.word 511
-.word 255
-.word 127
-.word 63
-.word 31
-.word 15
-.word 7
-.word 515
-.word 769
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-.word 778
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-.word 875
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-.word 219
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-.word 54
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-.word 96
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-.word 774
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-.word 705
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-.word 102
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-.word 424
-.word 724
-.word 362
-.word 693
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-.word 941
-.word 470
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-
-RVTEST_CODE_END
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index d0c6724..35fc99a 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -18,6 +18,7 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
   #undef SSTATUS_SPP
   #define SSTATUS_SPP MSTATUS_MPP
@@ -55,24 +56,24 @@ RVTEST_CODE_BEGIN
   TEST_CASE(11, x0, 0, nop)
 #endif
 
-  # Exit by doing a syscall.
-  TEST_CASE(12, x0, 1, scall)
+  RVTEST_PASS
 
   # We should only fall through to this if scall failed.
   TEST_PASSFAIL
 
 stvec_handler:
-  # Trapping on tests 11 and 12 is usually good news.
+  # Trapping on tests 10 and 11 is good news.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.
   li t0, 9
   beq TESTNUM, t0, privileged
   li t0, 10
   beq TESTNUM, t0, privileged
-  li t0, 11
-  beq TESTNUM, t0, syscall
 
-  # Trapping on other tests is bad news.
-  j fail
+  # catch RVTEST_PASS and kick it up to M-mode
+  csrr t0, scause
+  li t1, CAUSE_USER_ECALL
+  bne t0, t1, fail
+  RVTEST_PASS
 
 privileged:
   # Make sure scause indicates a lack of privilege.
@@ -85,15 +86,6 @@ privileged:
   csrw sepc, t0
   sret
 
-syscall:
-  # Make sure scause indicates a syscall.
-  csrr t0, scause
-  li t1, CAUSE_USER_ECALL
-  bne t0, t1, fail
-
-  # We're done.
-  j pass
-
 RVTEST_CODE_END
 
   .data
diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index db702d9..a97eecb 100644
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -18,6 +18,7 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
 #endif
 
diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S
index bf38434..99240be 100644
--- a/isa/rv64si/sbreak.S
+++ b/isa/rv64si/sbreak.S
@@ -18,6 +18,7 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
 #endif
 
diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 703de0b..f4752d1 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -18,6 +18,7 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
   #undef SSTATUS_SPP
   #define SSTATUS_SPP MSTATUS_MPP
@@ -29,9 +30,10 @@ RVTEST_CODE_BEGIN
   csrc sstatus, t0
   la t0, 1f
   csrw sepc, t0
-  eret
+  sret
 1:
 
+  li TESTNUM, 1
   scall
   j fail
 
diff --git a/isa/rv64uf/Makefrag b/isa/rv64uf/Makefrag
index c42b5f7..978084a 100644
--- a/isa/rv64uf/Makefrag
+++ b/isa/rv64uf/Makefrag
@@ -7,7 +7,6 @@ rv64uf_sc_tests = \
 	ldst move structural recoding \
 
 rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
-rv64uf_pt_tests = $(addprefix rv64uf-pt-, $(rv64uf_sc_tests))
 rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
 
-spike_tests += $(rv64uf_p_tests) $(rv64uf_pt_tests) $(rv64uf_v_tests)
+spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests)
diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag
index d8d21af..e839118 100644
--- a/isa/rv64ui/Makefrag
+++ b/isa/rv64ui/Makefrag
@@ -30,8 +30,6 @@ rv64ui_mc_tests = \
 	lrsc
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
-rv64ui_pt_tests = $(addprefix rv64ui-pt-, $(rv64ui_sc_tests))
-rv64ui_pm_tests = $(addprefix rv64ui-pm-, $(rv64ui_mc_tests))
 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
 
-spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_pt_tests) $(rv64ui_v_tests)
+spike_tests += $(rv64ui_p_tests) $(rv64ui_v_tests)