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| author | Tim Newsome <tim@sifive.com> | 2017-09-19 11:23:35 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-09-19 11:23:35 -0700 |
| commit | e087d97b130ec0a04c8d3498a66503c1746dadd3 (patch) | |
| tree | 1ba8ffb3ad3679c176b73ba2c3237a97b9ad8329 | |
| parent | 38fc7c6a96f47499b738835b0f01a42edf093d39 (diff) | |
| download | riscv-tests-e087d97b130ec0a04c8d3498a66503c1746dadd3.zip riscv-tests-e087d97b130ec0a04c8d3498a66503c1746dadd3.tar.gz riscv-tests-e087d97b130ec0a04c8d3498a66503c1746dadd3.tar.bz2 | |
Forgot to commit this earlier.
Fixes #77.
| -rw-r--r-- | debug/programs/init.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/debug/programs/init.h b/debug/programs/init.h new file mode 100644 index 0000000..9aaa398 --- /dev/null +++ b/debug/programs/init.h @@ -0,0 +1,20 @@ +#ifndef INIT_H +#define INIT_H + +#define MTIME (*(volatile long long *)(0x02000000 + 0xbff8)) +#define MTIMECMP ((volatile long long *)(0x02000000 + 0x4000)) + +#define csr_read(csr) \ +({ \ + register unsigned long __v; \ + __asm__ __volatile__ ("csrr %0, " #csr \ + : "=r" (__v)); \ + __v; \ +}) + +typedef void* (*trap_handler_t)(unsigned hartid, unsigned mcause, void *mepc, + void *sp); +void set_trap_handler(trap_handler_t handler); +void enable_timer_interrupts(); + +#endif |