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| author | Christopher Celio <celio@eecs.berkeley.edu> | 2018-04-30 17:03:50 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-04-30 17:03:50 -0700 |
| commit | 67500e2f200619bcd8ca3a8e5d396ea3021a7e27 (patch) | |
| tree | 40ed7936c5953c5ebc82c62526828d769dd535fb | |
| parent | 35a6b67f48782994d7a62cf46e0aef9190d5d7d9 (diff) | |
| download | riscv-tests-67500e2f200619bcd8ca3a8e5d396ea3021a7e27.zip riscv-tests-67500e2f200619bcd8ca3a8e5d396ea3021a7e27.tar.gz riscv-tests-67500e2f200619bcd8ca3a8e5d396ea3021a7e27.tar.bz2 | |
[rv64ua/lrsc] Initialize memory read out. (#135)
* [rv64ua/lrsc] Initialize memory read out.
Even though the load contents are discarded, this un-initialized memory value
can lead to a divergence for co-simulation between two different RISC-V designs.
* [rv64ua/lrsc] Use .skip instead of .align.
| -rw-r--r-- | isa/rv64ua/lrsc.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S index 11eb7de..14ef07d 100644 --- a/isa/rv64ua/lrsc.S +++ b/isa/rv64ua/lrsc.S @@ -35,7 +35,7 @@ TEST_CASE( 2, a4, 1, \ # TODO is this actually mandatory behavior? TEST_CASE( 3, a4, 1, \ la a0, foo; \ - add a1, a0, 1024; \ + la a1, fooTest3; \ lr.w a1, (a1); \ sc.w a4, a1, (a0); \ ) @@ -82,4 +82,6 @@ RVTEST_DATA_BEGIN coreid: .word 0 barrier: .word 0 foo: .word 0 +.skip 1024 +fooTest3: .word 0 RVTEST_DATA_END |