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| author | YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | 2022-10-27 00:47:22 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-26 09:47:22 -0700 |
| commit | fc8cb130c9289b6ba9377560342c6c3653f6f42b (patch) | |
| tree | 538f3b118aa256f03a958b92859d62cbd916208f | |
| parent | fb8ab0e8e2dc3e385105674b01be6fe1288b5426 (diff) | |
| download | riscv-tests-fc8cb130c9289b6ba9377560342c6c3653f6f42b.zip riscv-tests-fc8cb130c9289b6ba9377560342c6c3653f6f42b.tar.gz riscv-tests-fc8cb130c9289b6ba9377560342c6c3653f6f42b.tar.bz2 | |
Specify trigger type=2 in trigger.S (#425)
* Specify trigger type=2 in trigger.S
Previous tests implicitly assume triggers only support type=2. However,
a trigger may support multiple types, i.e., type=15. This commit
explicitly specifies type=2 in trigger.S to support type 15.
* Update debug/programs/trigger.S
Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
| -rw-r--r-- | debug/programs/trigger.S | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/debug/programs/trigger.S b/debug/programs/trigger.S index 2ccfd21..4b3da91 100644 --- a/debug/programs/trigger.S +++ b/debug/programs/trigger.S @@ -40,14 +40,15 @@ write_loop: j main_exit write_store_trigger: - li a0, (1<<6) | (1<<1) + /* 2<<60 is for RV64. 2<<28 is for RV32. That's safe because on RV64 bits 28 and 29 are 0. */ + li a0, (2<<60) | (2<<28) | (1<<6) | (1<<1) li a1, 0xdeadbee0 jal write_triggers la a0, data jal read_triggers write_load_trigger: - li a0, (1<<6) | (1<<0) + li a0, (2<<60) | (2<<28) | (1<<6) | (1<<0) li a1, 0xfeedac00 jal write_triggers la a0, data |