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author | liangzhen <zhen.liang@spacemit.com> | 2023-10-24 09:29:53 +0800 |
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committer | liangzhen <zhen.liang@spacemit.com> | 2023-10-24 09:29:53 +0800 |
commit | aa15f70c071a03b428621990142f6c049a656526 (patch) | |
tree | 57b4de30f25448454476fd93cd5dcc5d43336b55 /.gitmodules | |
parent | d020e2069a9f6a9c0e875f23f0f4aababea9fbf0 (diff) | |
download | riscv-tests-aa15f70c071a03b428621990142f6c049a656526.zip riscv-tests-aa15f70c071a03b428621990142f6c049a656526.tar.gz riscv-tests-aa15f70c071a03b428621990142f6c049a656526.tar.bz2 |
Support instruction count limit in IcountTest
This is taking into account that the hardware limits count to 1.
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
Diffstat (limited to '.gitmodules')
0 files changed, 0 insertions, 0 deletions