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authorAndrew Waterman <aswaterman@gmail.com>2025-06-13 16:33:08 -0700
committerGitHub <noreply@github.com>2025-06-13 16:33:08 -0700
commitb5ba87097c42aa41c56657e0ae049c2996e8d8d8 (patch)
tree33da40f3b13140c3e4d947a0a3ceb709451d1258
parent7b7074aed2db4f4445205efa5311ba9009f45fb7 (diff)
parent1f9e2fe2dc8cf462f54bb5d734e8ff845f2ac63d (diff)
downloadriscv-tests-master.zip
riscv-tests-master.tar.gz
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Merge pull request #624 from riscv-software-src/ziccidHEADmaster
Add Ziccid test
-rw-r--r--isa/Makefile6
-rw-r--r--isa/rv64uziccid/Makefrag9
-rw-r--r--isa/rv64uziccid/ziccid.S48
3 files changed, 61 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile
index e3b6719..b1f0c2a 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -13,6 +13,7 @@ include $(src_dir)/rv64um/Makefrag
include $(src_dir)/rv64ua/Makefrag
include $(src_dir)/rv64uf/Makefrag
include $(src_dir)/rv64ud/Makefrag
+include $(src_dir)/rv64uziccid/Makefrag
include $(src_dir)/rv64uzfh/Makefrag
include $(src_dir)/rv64uzba/Makefrag
include $(src_dir)/rv64uzbb/Makefrag
@@ -59,10 +60,10 @@ vpath %.S $(src_dir)
$(RISCV_OBJDUMP) $< > $@
%.out: %
- $(RISCV_SIM) --isa=rv64gch_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
+ $(RISCV_SIM) --isa=rv64gch_ziccid_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
%.out32: %
- $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
+ $(RISCV_SIM) --isa=rv32gc_ziccid_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
define compile_template
@@ -108,6 +109,7 @@ $(eval $(call compile_template,rv64um,-march=rv64g -mabi=lp64))
$(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64))
$(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64))
$(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64uziccid,-march=rv64g -mabi=lp64))
$(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64))
$(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64))
$(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64))
diff --git a/isa/rv64uziccid/Makefrag b/isa/rv64uziccid/Makefrag
new file mode 100644
index 0000000..0a16a0f
--- /dev/null
+++ b/isa/rv64uziccid/Makefrag
@@ -0,0 +1,9 @@
+#=======================================================================
+# Makefrag for rv64uziccid tests
+#-----------------------------------------------------------------------
+
+rv64uziccid_sc_tests = \
+ ziccid \
+
+rv64uziccid_p_tests = $(addprefix rv64uziccid-p-, $(rv64uziccid_sc_tests))
+rv64uziccid_v_tests = $(addprefix rv64uziccid-v-, $(rv64uziccid_sc_tests))
diff --git a/isa/rv64uziccid/ziccid.S b/isa/rv64uziccid/ziccid.S
new file mode 100644
index 0000000..1e3256a
--- /dev/null
+++ b/isa/rv64uziccid/ziccid.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ziccid.S
+#-----------------------------------------------------------------------------
+#
+# Test Ziccid eventuality property.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ la t0, insn
+ li t1, 0x00100513 # li a0, 1
+ li t2, 0x00000513 # li a0, 0
+
+ sw t2, (t0)
+ fence.i
+
+ li a1, 100
+loop:
+ .balign 2
+insn:
+ .word 0
+
+ addi a1, a1, -1
+ bnez a1, 1f
+ # modify instruction on 100th iteration
+ sw t1, (t0)
+1:
+ # break out of loop if the modified instruction is executed
+ beqz a0, loop
+
+ TEST_CASE(2, x0, 0, nop)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END