From 928743b105becf2bedf704b97d220825690c0c52 Mon Sep 17 00:00:00 2001 From: YenHaoChen Date: Fri, 2 Feb 2024 14:14:28 +0800 Subject: Teach Sstc to respect xenvcfg.STCE When menvcfg.STCE=0, mip.STIP reverts to its defined behavior as if unsupporting Sstc extension. When henvcfg.STCE=0, mip.VSTIP reverts to its defined behavior as if unsupporting Sstc extension. [https://github.com/riscv/riscv-time-compare/issues/5] The previous Sstc implementation does not respect the xenvcfg.STCE. In other words, the Sstc may assert mip.STIP (mip.VSTIP) when menvcfg.STCE=0 (henvcfg.STCE=0), which is a misbehaving. --- riscv/csrs.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'riscv') diff --git a/riscv/csrs.cc b/riscv/csrs.cc index b76b496..f00f88e 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1075,7 +1075,8 @@ void time_counter_csr_t::sync(const reg_t val) noexcept { if (proc->extension_enabled(EXT_SSTC)) { const reg_t mip_val = (shadow_val >= state->stimecmp->read() ? MIP_STIP : 0) | (shadow_val + state->htimedelta->read() >= state->vstimecmp->read() ? MIP_VSTIP : 0); - state->mip->backdoor_write_with_mask(MIP_STIP | MIP_VSTIP, mip_val); + const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0); + state->mip->backdoor_write_with_mask(mask, mip_val); } } @@ -1533,7 +1534,8 @@ stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const } bool stimecmp_csr_t::unlogged_write(const reg_t val) noexcept { - state->mip->backdoor_write_with_mask(intr_mask, state->time->read() >= val ? intr_mask : 0); + const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0); + state->mip->backdoor_write_with_mask(mask, state->time->read() >= val ? intr_mask : 0); return basic_csr_t::unlogged_write(val); } -- cgit v1.1