From 858ffef27f7a6ed117c58326ea81b0d1654ad3a2 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 30 Mar 2020 11:34:32 -0700 Subject: Assert that debug_module is initialized correctly. (#437) This would have prevented the regression in #409. --- riscv/debug_module.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'riscv/debug_module.cc') diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index ef26b28..5c7d2f1 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -77,6 +77,7 @@ debug_module_t::~debug_module_t() void debug_module_t::reset() { + assert(sim->nprocs() > 0); for (unsigned i = 0; i < sim->nprocs(); i++) { processor_t *proc = sim->get_core(i); if (proc) -- cgit v1.1