From a1506ec006bad9c727652a5f7fbfe91c52572565 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 20 Aug 2024 09:11:27 -0700 Subject: For mcontrol6, default to BEFORE timing. The existing implementation would end up using AFTER even for instruction execute and data store triggers, which is not desirable. --- riscv/triggers.cc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 9eac968..5f3ffee 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -265,7 +265,14 @@ bool mcontrol_common_t::legalize_timing(reg_t val, reg_t timing_mask, reg_t sele return TIMING_AFTER; if (get_field(val, execute_mask)) return TIMING_BEFORE; - return get_field(val, timing_mask); + if (timing_mask) { + // Use the requested timing. + return get_field(val, timing_mask); + } else { + // For mcontrol6 you can't request a timing. Default to before since that's + // most useful to the user. + return TIMING_BEFORE; + } } reg_t mcontrol6_t::tdata1_read(const processor_t * const proc) const noexcept { -- cgit v1.1