From 3fbe5ad91f124c72b25873b65b712b099fe58486 Mon Sep 17 00:00:00 2001
From: Chih-Min Chao <chihmin.chao@sifive.com>
Date: Thu, 4 Jun 2020 01:45:04 -0700
Subject: rvv: fix compilation warning

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
---
 riscv/decode.h   | 12 ++++++------
 riscv/execute.cc |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/riscv/decode.h b/riscv/decode.h
index dbe6f0e..425a68e 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1839,9 +1839,9 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
                 softfloat_exceptionFlags |= softfloat_flag_invalid; \
                 set_fp_exceptions; \
               } \
-              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = defaultNaNF16UI; \
+              P.VU.elt<uint16_t>(rd_num, 0, true) = defaultNaNF16UI; \
             } else { \
-              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \
+              P.VU.elt<uint16_t>(rd_num, 0, true) = vd_0.v; \
             } \
           } \
           break; \
@@ -1852,9 +1852,9 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
                 softfloat_exceptionFlags |= softfloat_flag_invalid; \
                 set_fp_exceptions; \
               } \
-              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = defaultNaNF32UI; \
+              P.VU.elt<uint32_t>(rd_num, 0, true) = defaultNaNF32UI; \
             } else { \
-              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \
+              P.VU.elt<uint32_t>(rd_num, 0, true) = vd_0.v; \
             } \
           } \
           break; \
@@ -1865,9 +1865,9 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
                 softfloat_exceptionFlags |= softfloat_flag_invalid; \
                 set_fp_exceptions; \
               } \
-              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = defaultNaNF64UI; \
+              P.VU.elt<uint64_t>(rd_num, 0, true) = defaultNaNF64UI; \
             } else { \
-              P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \
+              P.VU.elt<uint64_t>(rd_num, 0, true) = vd_0.v; \
             } \
           } \
           break; \
diff --git a/riscv/execute.cc b/riscv/execute.cc
index b18a55d..e5513d8 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -110,7 +110,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn)
         fprintf(log_file, " e%ld %s%ld l%ld",
                 p->VU.vsew,
                 p->VU.vflmul < 0 ? "mf" : "m",
-                p->VU.vflmul < 0 ? (1 / p->VU.vflmul) : p->VU.vflmul,
+                p->VU.vflmul < 0 ? (reg_t)(1 / p->VU.vflmul) : (reg_t)p->VU.vflmul,
                 p->VU.vl);
         show_vec = true;
     }
-- 
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