aboutsummaryrefslogtreecommitdiff
path: root/spike_main
AgeCommit message (Collapse)AuthorFilesLines
2023-07-09build: Link spike binaries with --whole-archivewhole-archiveJerry Zhao1-0/+2
The --extlib and --extension features require runtime dynamic linking of externally compiled libraries. Spike main must make all symbols of libriscv available for those libraries.
2023-06-20devices: Switch plugin device interface to use device_factory_tJerry Zhao1-49/+9
Plugins should now implement and register a device_factory_t to configure how that device should be parsed from a FDT, and an optional default DTS string. This drops support for command-line flag-based device configuration
2023-06-20sim_t: change plugin_devices to a vec of shared_ptrsJerry Zhao1-5/+2
2023-03-30Fix --bootargs default value in spike usage help() functionJulien Olivain1-1/+2
Commit 191634d285 changed the default kernel boot args from "console=hvc0 earlycon=sbi" to "console=ttyS0 earlycon", but didn't updated the spike usage help() function. This commit introduces a new macro DEFAULT_KERNEL_BOOTARGS in order to have a single definition. This macro is used everywhere in dts.cc and spike.cc help() function. Signed-off-by: Julien Olivain <ju.o@free.fr>
2023-02-27Improve input validation for --hartids flagAndrew Waterman1-0/+18
Disallow negative hartids, repeated hartids, and empty lists.
2023-02-27Use size_t, rather than int, for hartidsAndrew Waterman2-5/+5
They aren't signed quantities.
2023-01-27Remove dirty_enabled from cfg_tAaron Durbin2-2/+0
The addition of Svadu support and removal of --mmu-dirty command line flag results in the dirty_enabled configuration state no longer being used. Remove the remnants of this state.
2023-01-27Remove --mmu-dirty command line flagAaron Durbin1-2/+0
With the addition of Svadu support, the --mmu-dirty flag no longer controls behavior of A/D updates to PTEs. Remove the flag.
2023-01-18Add --triggers flag to select number of triggersJerry Zhao1-0/+2
2023-01-18Add trigger_count field to cfg_tJerry Zhao2-2/+4
2023-01-10improve merge_mem_regions to handle memory region covering the whole 64-bit ↵Parshintsev Anatoly1-0/+24
address space
2023-01-09simplify check_mem_overlap by utilizing get_inclusive_end of mem_cfg_tParshintsev Anatoly1-4/+1
2023-01-09simplify merge_mem_regions by utilizing get_inclusive_end() of mem_cfg_tParshintsev Anatoly1-3/+3
this is to properly handle potential 64-bit overflow in (base + size) expression
2023-01-09get_inclusive_end implementation for mem_cfg_tParshintsev Anatoly1-3/+2
The method can simplify proper processing of sitiations when (base + size) overflows 64-bit interger.
2023-01-09implement get_size() getter for mem_cfg_t objectParshintsev Anatoly1-7/+7
NFT. We also mark `base` and `size` fields as private.
2023-01-09implement get_base() getter for mem_cfg_t objectParshintsev Anatoly1-10/+10
NFC. The intention is for `base` and `size` fields of mem_cfg_t to be private members. This is the fist part of this commit.
2023-01-04Add --mmu-dirty runtime flagJerry Zhao1-0/+2
2023-01-04Add cfg_t field to enable PTE dirtyingJerry Zhao2-0/+2
2023-01-03Add --[no-]misaligned command-line optionsAndrew Waterman2-0/+4
They don't do anything yet.
2023-01-03Pass cfg object to processor_t constructorAndrew Waterman1-1/+12
This reduces boilerplate as we add additional options.
2022-12-22Remove non-installed header lists from Makefile fragmentsAndrew Waterman1-2/+0
It's just dead code. (Dependences on headers are auto-generated as `.d` files.)
2022-12-15Add config.h includes directly to source files instead of relying on header ↵Jerry Zhao2-0/+2
chaining This step is to ensure that removing config.h out of headers will not cause regressions.
2022-12-15Rename memif_endianness_t to endianness_tJerry Zhao2-3/+3
2022-12-13Move boost asio socket interface to socketif_tJerry Zhao1-26/+1
This reduces dependencies on config.h in sim.h
2022-11-30Reimplement memory merging routinesParshintsev Anatoly1-22/+41
This commit simplifies the codebase by factoring out memory merging and intersection checking routines into separate functions. This allows us to check for corner cases more easily.
2022-11-16Merge pull request #1119 from aap-sc/aap-sc/max_pa_restrictionAndrew Waterman1-5/+24
Do not allow memory regions larger than (1ull << MAX_PADDR_BITS)
2022-11-16Only allow memory regions that are less than (1ull << MAX_PADDR_BITS)Parshintsev Anatoly1-1/+21
Other regions are inaccessible to the hardware being modeled
2022-11-15get rid of redundant casts during mem layout processingParshintsev Anatoly1-4/+3
2022-10-25Remove set_target_endianness | add --big-endian flagJerry Zhao2-1/+4
Set target endianess in constructors
2022-10-20Set 16..4096-byte bound on cache-block sizeAndrew Waterman1-2/+5
16 B suffices to subsume all aligned accesses (including the Q extension). Spike does not actually rely on this property, but in some real systems, it is impractical to guarantee atomicity across cache lines. 4096 B suffices to prevent cache lines from spanning pages (which would require multiple TLB accesses). This one is a bug fix, since we were not performing multiple TLB accesses in this case.
2022-10-14Support command-line configuration of number of pmpregionsJerry Zhao1-0/+3
2022-10-14Report error if an unsupported memory configuration is detectedParshintsev Anatoly1-3/+8
2022-10-07Add --dm-no-abstract-fpr option.Tim Newsome1-1/+5
Previously FPRs could always be accessed using abstract commands. I need this to get coverage of some OpenOCD code that I broke. (See https://github.com/riscv/riscv-openocd/pull/745)
2022-10-04Suppress unused-variable warnings in spike mainAndrew Waterman1-1/+1
2022-10-04Fix or work around other unused-parameter warnings in ancillary programsAndrew Waterman2-5/+6
2022-10-04Suppress unused-parameter warnings in spike mainAndrew Waterman1-16/+16
2022-09-23Build and install lib and header dependencies for HammerJerin Joy1-0/+2
https://github.com/rivosinc/hammer Signed-off-by: Jerin Joy <joy@rivosinc.com>
2022-08-10Add missed decription for log-commits optionWeiwei Li1-0/+1
2022-04-30Add missing description of --dtb in --help messageAndrew Waterman1-0/+1
2022-04-12Move real_time_clint into cfg_tRupert Swarbrick1-4/+4
2022-04-12Move varch into cfg_tRupert Swarbrick1-3/+3
2022-04-12Remove nprocs from cfg_tRupert Swarbrick1-7/+8
Now we have hartids, we can remove nprocs so that we have a single source of truth.
2022-04-12Move hartids into cfg_tRupert Swarbrick1-11/+17
The only slightly difficult thing here is that hartids will always be considered "overridden" by the time we get to sim_t::sim_t (either overridden by a command line argument, or overridden when we set default hartids just before the constructor). To allow downstream code to distinguish between "I picked IDs 0, 1, 2, 3 because the user asked for 4 processors" and "The user explicitly asked for IDs 0, 1, 2, 3", we have an extra explicit_hartids field.
2022-04-12Move the "default hartids" logic from sim.cc into spike.ccRupert Swarbrick1-0/+16
This moves another part of the "configuration" out of the generic sim.cc code.
2022-04-12Slightly refactor --hartids parsing in spike.ccRupert Swarbrick1-13/+16
We now parse to a std::vector<int> and then set the "hartids" variable to the result. There is a slight functional change here, in that if you pass "--hartids 1,2,3 --hartids 4,5", you'll now get 2 cores with ids of 4,5 rather than 5 cores with ids of 1,2,3,4,5. This is what most tools do with repeated command line arguments and I suspect the old behaviour was actually by accident!
2022-04-12Move start_pc into cfg_tRupert Swarbrick1-3/+2
2022-04-11Change processor_t to hold a pointer to an isa_parser_t (#973)Rupert Swarbrick1-1/+1
Before, it had another copy, which is a little unnecessary.
2022-04-11Split mem layout computation in spike.cc (#957)Rupert Swarbrick1-25/+36
The motivation here is mostly to enable a refactoring where the memory layout (sans allocated memory) gets passed to DTS/DTB code before we ever allocate anything. But it turns out to make merge_overlapping_memory_regions a bit simpler, which is an added bonus.
2022-03-18Fold priv parameter into cfg_tRupert Swarbrick1-4/+4
2022-03-18Fold isa parameter into cfg_tRupert Swarbrick1-4/+5