| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2018-01-03 | Add some missing RVC instructions to disassembler | Andrew Waterman | 1 | -0/+3 |
| 2017-11-06 | Implement Q extension for disassembler (#153) | Kito Cheng | 1 | -0/+36 |
| 2017-11-03 | Fix disassembly of c.li 0 | Andrew Waterman | 1 | -1/+1 |
| 2017-08-10 | Correct c.li and c.lui disassembly (#118) | Palmer Dabbelt | 1 | -2/+2 |
| 2017-04-25 | FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X | Andrew Waterman | 1 | -2/+2 |
| 2017-04-25 | Remove hret instruction | Andrew Waterman | 1 | -1/+0 |
| 2016-06-29 | Disassemble RVC instructions based on XLEN | Andrew Waterman | 1 | -8/+18 |
| 2016-06-03 | Minor usability improvements (#48) | neuschaefer | 1 | -1/+6 |
| 2016-04-28 | Remove MTIME[CMP]; add RTC device | Andrew Waterman | 1 | -1/+0 |
| 2016-04-19 | Split ERET into URET, SRET, HRET, MRET | Andrew Waterman | 1 | -3/+6 |
| 2015-10-20 | Update to hopefully final RVC 1.9 encoding | Andrew Waterman | 1 | -2/+0 |
| 2015-10-05 | more work towards RVC 1.8 | Andrew Waterman | 1 | -9/+2 |
| 2015-10-02 | work towards rvc 1.8 | Andrew Waterman | 1 | -3/+17 |
| 2015-09-04 | Move towards RVC v1.8 | Andrew Waterman | 1 | -10/+4 |
| 2015-05-31 | New RV64C proposal | Andrew Waterman | 1 | -19/+63 |
| 2015-03-30 | Implement RVC draft | Andrew Waterman | 1 | -0/+115 |
| 2015-01-04 | canonicalize assembler pseudo-ops | Andrew Waterman | 1 | -2/+11 |
| 2015-01-04 | Disassemble jalr x0, x1, 0 as ret | Andrew Waterman | 1 | -1/+1 |
| 2014-12-20 | Support building from within root directory | Andrew Waterman | 1 | -0/+395 |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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