| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-06-28 | Fix insn interactive command (catch/print trap, use proper access func) | abejgonzalez | 1 | -29/+30 | |
| 2024-06-26 | Add insn cmds to interactive debug mode | abejgonzalez | 2 | -19/+57 | |
| 2024-06-21 | Vector-fp instructions depend on zve, not F/D | Jerry Zhao | 2 | -10/+12 | |
| 2024-06-21 | Remove all --varch parsing | Jerry Zhao | 5 | -70/+0 | |
| 2024-06-21 | Switch to Zvl/Zve parsing from isa_parser, instead of varch | Jerry Zhao | 1 | -1/+4 | |
| 2024-06-21 | Disallow any vector, not just V, when no __int128 type is present | Jerry Zhao | 1 | -1/+1 | |
| 2024-06-21 | Relax require_vector check for misa.V | Jerry Zhao | 1 | -2/+0 | |
| 2024-06-21 | Relax mstatus.vs dependency on full V | Jerry Zhao | 2 | -1/+5 | |
| 2024-06-21 | Relax vector_csr dependency on 'V' | Jerry Zhao | 1 | -4/+0 | |
| 2024-06-21 | Relax has_fs dependency on misa.v | Jerry Zhao | 1 | -2/+1 | |
| isa_parser should already require any Zvef or Zved extensions imply F/D | |||||
| 2024-06-21 | Add accessors to isa_parser's VLEN/ELEN | Jerry Zhao | 1 | -0/+3 | |
| 2024-06-21 | Add isa_parser parsing for zvl/zve | Jerry Zhao | 1 | -0/+4 | |
| 2024-06-20 | Merge pull request #1690 from riscv-software-src/fix-warnings | Jerry Zhao | 2 | -17/+17 | |
| Fix a few compile warnings | |||||
| 2024-06-13 | Adding Zilsd and Zcmlsd extensions (Load/store pair for RV32) | Christian Herber | 8 | -16/+63 | |
| 2024-06-12 | Fix a few compile warnings | Andrew Waterman | 2 | -17/+17 | |
| 2024-06-11 | Validate contents of overlap list in CI | Andrew Waterman | 1 | -13/+32 | |
| 2024-06-11 | Separate RV32 and RV64 C instructions into separate files | Andrew Waterman | 10 | -33/+31 | |
| 2024-06-11 | Improve hit rate of opcode cache to compensate for not mutating insn list | Andrew Waterman | 2 | -17/+58 | |
| 2024-06-11 | Compensate for perf loss of not mutating insn list by presorting it | Andrew Waterman | 1 | -7/+7 | |
| 2024-06-11 | Keep potentially overlapping instructions in order at head of list | Andrew Waterman | 1 | -20/+32 | |
| 2024-06-11 | Preserve the ordering of the instruction list | Andrew Waterman | 1 | -22/+2 | |
| 2024-06-11 | Add comments to overlap list | Andrew Waterman | 1 | -0/+9 | |
| 2024-06-11 | Refine Zicfiss overlap list | Andrew Waterman | 1 | -2/+5 | |
| We get better error checking if we list only the more specific instructions and omit the more general ones (mop.r.N/mop.rr.N). | |||||
| 2024-06-11 | Remove unnecessary instructions from overlap list | Andrew Waterman | 1 | -11/+0 | |
| - c.fsdsp need not be listed since cm.push etc. are listed - mop.r.28/mop.rr.7 don't have corresponding files in riscv/insns/ - the rest are just erroneous | |||||
| 2024-06-11 | Add missing instructions to Makefile | Andrew Waterman | 1 | -0/+4 | |
| 2024-06-11 | triggers: implement tcontrol | YenHaoChen | 5 | -1/+9 | |
| Implement Debug spec Section 5.7.6. Trigger Control (tcontrol). This commit lets tcontrol be read-only 0 if number of triggers is 0. | |||||
| 2024-05-31 | Avoid checking ELP before every instruction fetch | Andrew Waterman | 6 | -13/+12 | |
| Serialize after setting ELP. That way, we can hoist the check outside of the main simulation loop. | |||||
| 2024-05-31 | No need to check if Zicfilp is enabled before checking ELP | Andrew Waterman | 1 | -3/+1 | |
| ELP will be zero if Zicfilp is not enabled. | |||||
| 2024-05-27 | Merge pull request #1678 from rbuchner-aril/rbuchner/vxsat-write | Andrew Waterman | 1 | -0/+2 | |
| Require vector extension when attempting vxsat writes | |||||
| 2024-05-27 | Require vector extension when attempting vxsat writes | rbuchner | 1 | -0/+2 | |
| Accidentally removed in c9468f6e02. See #1660. | |||||
| 2024-05-26 | Merge pull request #1677 from YenHaoChen/pr-vector-reduction | Andrew Waterman | 1 | -4/+4 | |
| vector: Not logging write of reduction instructions when vl = 0 | |||||
| 2024-05-24 | vector: Not logging write of reduction instructions when vl = 0 | YenHaoChen | 1 | -4/+4 | |
| The spec says: "If vl=0, no operation is performed and the destination register is not updated." in Section 14. Vector Reduction Operations. The commit proposes setting the variable is_write to false when vl = 0, which means not logging the write. | |||||
| 2024-05-23 | zicflip: fix [ms]ret behavior | Chih-Min Chao | 2 | -2/+2 | |
| Based on Spec chapter 3.5 "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively. When executing an xRET instruction, if xPP holds the value y, then ELP is set to the value of xPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED." The change follow the last statement after semicolon "xPELP is set to NO_LP_EXPECTED" Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2024-05-22 | triggers: introduce tinfo.version | YenHaoChen | 1 | -1/+2 | |
| 2024-05-22 | triggers: implement mcontrol6.hit | YenHaoChen | 1 | -1/+1 | |
| 2024-05-22 | triggers: refactor: add typedef enum { ... } hit_t for mcontrol6 | YenHaoChen | 2 | -7/+15 | |
| Avoid using private headers, e.g., debug_defines.h, in triggers.h | |||||
| 2024-05-22 | triggers: refactor: move mcontrol_common_t::hit to mcontrol_t::hit and ↵ | YenHaoChen | 2 | -2/+12 | |
| mcontrol6_t::hit Add mcontrol_common_t::set_hit() | |||||
| 2024-05-22 | triggers: refactor: update debug_defines.h | YenHaoChen | 2 | -1218/+1340 | |
| Update CSR_MCONTROL6_HIT to CSR_MCONTROL6_HIT0 Include CSR_TINFO_VERSION* macros | |||||
| 2024-05-21 | triggers: remove mcontrol6.timing (implement suggested trigger timings) | YenHaoChen | 1 | -2/+5 | |
| 2024-05-06 | Add Zawrs extension | Ved Shanbhogue | 4 | -0/+13 | |
| 2024-05-03 | Zfa: fix: fmaxm.q requires Q instead of D extension | YenHaoChen | 1 | -1/+1 | |
| 2024-05-01 | Update encoding.h | Andrew Waterman | 1 | -1116/+37 | |
| 2024-05-01 | Remove Zbpbo, Zpn, and Zpsfoperand implementation | Andrew Waterman | 334 | -3013/+24 | |
| 2024-04-30 | Support per-device arguments and device factory reuse | LIU Yu | 6 | -26/+28 | |
| As proposed in #1652, we made the following changes to MMIO device (factory) plugin API, to mitigate current limitations and facilitate factory reuse. - removed `sargs` from `device_factory_t`, and introduced a new type alias `device_factory_sargs_t` to capture `<device_factory_t *, sargs>` pairs, this is used to instantiate sim_t instances; - changed the signature of `device_factory_t::generate_fdt` and `device_factory_t::parse_from_fdt` to take on an extra `sargs` argument, for instantiating devices with per-device arguments; - made `device_factory_t` const and potentially resuable across multiple `sim_t` instances. | |||||
| 2024-04-29 | Merge pull request #1648 from YenHaoChen/pr-hstateen | Andrew Waterman | 2 | -6/+10 | |
| Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0 | |||||
| 2024-04-29 | Merge pull request #1579 from tebartsch/plic-threshold-masking | Andrew Waterman | 1 | -0/+9 | |
| PLIC: Implement threshold masking | |||||
| 2024-04-29 | add hlvx pmp protect to fix issue 1557 | xinyuwang-sifive | 4 | -9/+9 | |
| 2024-04-23 | Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0 | YenHaoChen | 2 | -6/+10 | |
| The specification states that writes to read-only bits in a RW CSR are ignored. The hstateen*[n] bits are read-only when mstateen*[n]=0. This PR proposes ignoring writes to read-only hstateen*[n] bits when mstateen*[n]=0 instead of writing the bits to 0. | |||||
| 2024-04-18 | Add Zicfiss extension from CFI extension, v0.4.0 | SuHsien Ho | 22 | -8/+194 | |
| 1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name. 2. Add new software exception with tval 3 for shadow stack. 3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d. 4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding. 5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page. 6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag. 7. Check special pte(xwr=010) of SS page. | |||||
| 2024-04-17 | Merge pull request #1595 from Siudya/until-paddr | Andrew Waterman | 1 | -2/+4 | |
| Interaction: Support until-mem operation on physical memory space | |||||
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