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2023-07-05Merge pull request #1394 from riscv-software-src/unavailableAndrew Waterman2-8/+43
Let debugger control hart availability
2023-07-05Let debugger control hart availabilityTim Newsome2-8/+43
This change lets me test OpenOCD's behavior when harts become available. It only affects how things look to the debugger. Harts that are "unavailable" still execute code as usual. Control is implemented through the 2 LSBs of the DMCUSTOM register in the Debug Module.
2023-07-02sim_t: Add sim_t::add_device() APIJerry Zhao2-4/+8
This is public so libspike users can precisely configure the device bus without going through the DTS interface
2023-06-23triggers: icount: not to decrease on firing icount trigger with Debug Mode ↵YenHaoChen1-1/+1
action The icount decreases on firing beakpoint action but not on entering Debug Mode action. Reference: https://github.com/riscv/riscv-debug-spec/issues/842
2023-06-21Merge pull request #1338 from aap-sc/aap-sc/sb_read_write_fixupAndrew Waterman1-12/+16
fixup sb_write/sb_read to handle exceptions
2023-06-20debug: Remove debug_module_t::add_device, its redundantJerry Zhao3-7/+1
2023-06-20devices: Switch plugin device interface to use device_factory_tJerry Zhao7-153/+22
Plugins should now implement and register a device_factory_t to configure how that device should be parsed from a FDT, and an optional default DTS string. This drops support for command-line flag-based device configuration
2023-06-20ns16550_t: ns16550 should parse interrupt id from the fdtJerry Zhao3-4/+15
2023-06-20dts: Expose fdt_get_node_addr_size function in headerJerry Zhao2-2/+4
2023-06-20dts_t: Add dts.h to list of installed headersJerry Zhao2-1/+1
2023-06-20device_t: device_factories should be constJerry Zhao2-8/+8
2023-06-20sim_t: Move dts device node construction/parsing to device_factoriesJerry Zhao3-85/+46
2023-06-20device_t: Add device_factory_t's for ns16550/clint/plicJerry Zhao3-0/+105
2023-06-20device_t: Add device_factory_tJerry Zhao1-0/+19
This class should implement conditional fdt-based device instantiation, as well as adding device nodes to the dts
2023-06-20sim_t: Add sim_t::get_intctrlJerry Zhao1-0/+1
2023-06-20Inline make_dtb into sim_t constructorJerry Zhao2-36/+29
make_dtb is only called here, this simplifies later work towards refactoring device DTS node generation
2023-06-20dts: void* fdt arg to parse_fdt should be constJerry Zhao2-20/+20
2023-06-20devices: Pass const pointers to sim_t to clint/plicJerry Zhao3-5/+5
2023-06-20ns16550_t: remove unused bus_t memberJerry Zhao3-5/+4
2023-06-20sim_t: Make static consts public membersJerry Zhao1-3/+4
2023-06-20sim_t: Merge sim_t::plugin_devices with sim_t::devicesJerry Zhao2-3/+3
2023-06-20sim_t: change plugin_devices to a vec of shared_ptrsJerry Zhao2-4/+4
2023-06-20sim_t: Remove boot_rom/ns16550 members of sim_tJerry Zhao2-5/+3
These are redundant with sim_t::devices
2023-06-20sim_t: Tick all devices, not just clint and ns16550Jerry Zhao1-2/+1
2023-06-20clint: Change clint_t::increment to override abstract_device_t::tick(rtc_ticks)Jerry Zhao5-10/+13
2023-06-20sim_t: Add list of ptrs to devices to sim_tJerry Zhao2-0/+5
2023-06-20sim_t: change devices to shared_ptrsJerry Zhao1-4/+4
2023-06-20device_t: Add missing overrides to derived abstract_device_t classesJerry Zhao1-13/+13
2023-06-19Zvk: Implement Zvksh, vector SM3 Hash FunctionEric Gouriou4-0/+151
Implement the Zvksh sub-extension, "ShangMi Suite: SM3 Hash Function Instructions": - vsm3me.vv, message expansion, - vsm3c.vi, compression rounds. This also introduces a SM3 specific header for common logic. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Albert Jakieła <aja@semihalf.com> Co-authored-by: Kornel Dulęba <mindal@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvksed, vector SM4 Block CipherEric Gouriou6-1/+206
Implement the Zvksed sub-extension, "ShangMi Suite: SM4 Block Cipher": - vsm4k.vi, vector SM4 key expansion, - vsm4r.{vs,vv}, vector SM4 rounds. This also introduces a header for common vector SM4 logic. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Albert Jakieła <aja@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvkned, vector AES single roundEric Gouriou13-0/+786
Implement the Zvkned extension, "NIST Suite: Vector AES Encryption & Decryption (Single Round)". - vaeskf1.vi: AES forward key scheduling, AES-128. - vaeskf2.vi: AES forward key scheduling, AES-256. - vaesz.vs: AES encryption/decryption, 0-th round. - vaesdm.{vs,vv}: AES decryption, middle rounds. - vaesdf.{vs,vv}: AES decryption, final round. - vaesem.{vs,vv}: AES encryption, middle rounds. - vaesef.{vs,vv}: AES encryption, final round. An extension specific header containing common logic is added. Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvknh[ab], NIST Suite: Vector SHA-2Eric Gouriou5-0/+348
Implement the instructions part of the Zvknha and Zvknhb sub-extensions: - vsha2ms.vv, message schedule - vsha2ch.vv / vsha2cl.vv, compression rounds A header files for common macros is added. Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvkg, Vector GCM/GMAC instructionEric Gouriou4-2/+89
Implement the proposed instruction in Zvkg, vghmac.vv, Vector Carryless Multiply Accumulate over GHASH Galois-Field. The instruction performs one step of GHASH routine as described in "NIST Special Publication 800-38D" a.k.a the AES-GCM specification. The logic was written to closely track the pseudo-code in the Zvk specification. Signed-off-by: Eric Gouriou <ego@rivosinc.com> Co-authored-by: Kornel Duleba <mindal@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvbc extension, vectory carryless multiplactionEric Gouriou5-0/+87
Implement the Zvbc instructions - vclmul.{vv,vx}, vector carryless multiply low - vclmulh.{vv,vx}, vector carryless multiply high Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvbb, Vector Bit-manipulation for CryptographyEric Gouriou18-0/+262
Implement the proposed instructions in Zvbb: - vandn.{vv,vx}, vector bitwise and-not - vbrev.v, vector bit reverse in element - vbrev8.v, vector bit reverse in bytes - vrev8.v, vector byte reverse - vctz.v, vector count trailing zeros - vclz.v, vector count leading zeros - vcpop.v, vector population count - vrol.{vv,vx}, vector rotate left - vror.{vi,vv,vx}, vector rotate right - vwsll.{vi,vv,vx} vector widening shift left logical A new instruction field, 'zimm6', is introduced, encoded in bits [15, 19] and [26].. It is used by "vror.vi" to encode a shift immediate in [0, 63]. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Infrastructure for Zvk extensions, element group handlingEric Gouriou6-2/+1148
Introduce types and macros useful across multiple Zvk sub-extensions, including Zvbb and Zvbc. Those will be used by upcoming per-sub-extension commits. In particular we introduce "Element Group" types and loop macros handling those element groups. The concept of element group is described in <https://github.com/riscv/riscv-crypto/blob/master/doc/vector/riscv-crypto-vector-element-groups.adoc>. Note that the element group access method is not implemented for WORDS_BIGENDIAN setup. As such, isa_parser.cc is modified to emit an error when WORDS_BIGENDIAN is defined and extensions using element groups are enabled. Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: extensions parsingEric Gouriou3-1/+81
Zvk is the short name for the Vector Cryptography Instruction Set Extension Specification being defined at <https://github.com/riscv/riscv-crypto/tree/master/doc/vector>. This commit adds support for parsing/enabling the Zvk extensions (Zvbb, Zvbc, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, Zvkt) and the combo extensions (Zvkn, Zvknc, Zvkng, Zvks, Zvksc, Zvksg). This is an early commit in a series implementing Zvk. No instructions are actually defined here, only infastructure that will support the coming extensions. The encodings for Zvk instructions have some conflicts with Zpn encodings. This commit marks those Zpn instructions as overlapping, and adds checks to error out if conflicting extensions are enabled. Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19List extensions alphabetically in riscv_insn_listEric Gouriou1-16/+16
The previous order lacks any obvious logic. Alphabetical order, while making it difficult to create interesting groupings, makes it easy to find which extensions are compiled in. Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Implement Zacas extension.Gianluca Guida8-0/+102
2023-06-19regenerate enconding.hGianluca Guida1-1/+133
2023-06-19mmu: support load/store longer than 64-bits.Gianluca Guida1-2/+15
2023-06-19fesvr: support int128_t/uint128_tGianluca Guida1-5/+0
Also remove now duplicate definition for types.
2023-06-18isa parser: reject Xbitmanip extensionsAndrew Waterman2-34/+1
2023-06-18Remove Xbitmanip from instructions that belong to multiple extensionsAndrew Waterman14-30/+16
2023-06-18Remove instructions that belong only to XbitmanipAndrew Waterman47-390/+0
2023-06-18Add CMOV to overlap list, as it overlaps CZERO.EQZAndrew Waterman1-0/+1
2023-06-17Add test that ensures opcodes don't overlap unless explicitly specifiedAndrew Waterman2-1/+59
2023-06-17Add C.EBREAK, C.JALR, and C.JR to overlap listAndrew Waterman1-0/+3
This isn't a functional change; we just failed to notate that C.EBREAK and C.JALR overlap C.ADD, and C.JR overlaps C.MV.
2023-06-12Merge pull request #1376 from YenHaoChen/pr-cbo-regionAndrew Waterman1-1/+1
Fix: PMP checking region on CBO instructions
2023-06-12Fix PMP checking region of cache-block management instructionsYenHaoChen1-1/+1
The spec says "The PMP access control bits shall be the same for all physical addresses in the cache block [... else] the behavior of a CBO instruction is UNSPECIFIED." Thus, we only need to check the byte rs1 points to (instead of the entire cache block).
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