aboutsummaryrefslogtreecommitdiff
path: root/riscv
AgeCommit message (Collapse)AuthorFilesLines
2022-05-05Factor out P extension macros into their own headerfactor-out-macrosAndrew Waterman2-500/+507
No functional change.
2022-05-05Factor out V extension macros into their own headerAndrew Waterman2-2069/+2076
No functional change.
2022-05-05Merge pull request #983 from soberl/epmp_updates_2Scott Johnson5-13/+130
Implement Smepmp extension
2022-05-04Update pmpaddr_csr_t::access_ok() for ePMP on matching regionssoberl@nvidia.com1-5/+31
2022-05-04Update mmu_t::pmp_ok() for ePMP in case matching region is not foundsoberl@nvidia.com1-1/+5
2022-05-04Update csr access rules for ePMP on pmpaddr and pmpcfgsoberl@nvidia.com1-7/+31
2022-05-04Implement the new csr mseccfg for ePMP as dummysoberl@nvidia.com4-0/+63
2022-05-04Merge pull request #985 from riscv-software-src/trigger_hitAndrew Waterman2-11/+18
Implement mcontrol.hit bit
2022-05-04Fix the padding of register names in the log (#987)Shaked Flur1-1/+1
This fix print x5 as "x5 ", instead of "x 5".
2022-05-02Use MCONTROL_TYPE_MATCH macro instead of 2Tim Newsome1-1/+1
2022-05-02Implement mcontrol trigger hit bit.Tim Newsome2-1/+14
2022-04-22Remove mcontrol_t.hTim Newsome2-4/+1
It was removed from the spec a long time ago.
2022-04-22Remove maskmax as a variable.Tim Newsome2-3/+2
2022-04-22Remove mcontrol_t.type.Tim Newsome2-3/+2
It's not writable anyway.
2022-04-22Whitespace fix.Tim Newsome1-1/+0
2022-04-21Pass acutally_store from store_func to misaligned_storeRyan Buchner1-1/+1
In future, someone may expect this functionality.
2022-04-21Add actually_store tag to misaligned_store functionRyan Buchner1-2/+2
Is passed along to the contained store_func.
2022-04-21Modify store_func to throw fault if misaligned and require_alignment=trueRyan Buchner1-2/+4
2022-04-21Set require alignment to true on the 'fake' store in amo_func.Ryan Buchner1-1/+1
2022-04-21Add require_alignment tag to store_funcRyan Buchner1-1/+1
Will be used similarly as in load_func.
2022-04-14Merge pull request #975 from plctlab/plct-code-styleAndrew Waterman5-299/+321
add macro support for instructions with overlapping encodings and fix partial style problems
2022-04-14add support for overlap instructionsWeiwei Li4-6/+25
* add DECLARE_OVERLAP_INSN to bind instructions with extension * add overlap_list.h to contain the declare of all overlapping instructions * make func function for overlapping instruction return NULL when the coresponding extension(s) is not supported.
2022-04-14fix style problems in decode.h and processor.ccWeiwei Li2-293/+296
2022-04-13Merge pull request #954 from rswarbrick/more-cfgAndrew Waterman3-28/+29
Move a few more configuration arguments into cfg_t
2022-04-13Adjust indentation in store_slow_path and store_funcRyan Buchner2-18/+18
Didn't want to make change in previous commit to isolate the change.
2022-04-13Skip storing in store_func if actually_store is false, add a fake store at ↵Ryan Buchner2-1/+8
start of AMO. This includes skipping store in store_slow_path. Is okay to skip the mmio_store part too, since the access_fault for mmio_failure will be caught on the actual store. The ordering for the mmio_access fault is irrelevant since it will occur after the TW faults, and load faults are converted to store faults. Will catch any faults from the access but won't perform a store. Since store permissions can only be granted if read permissions exist, any store faults will occur before or at the same time as a load fault. Thus this store permissions check is sufficient for properly catching the faults in an Amo access TW.
2022-04-12Add actually_store tag to store_func and store_slow_pathRyan Buchner2-4/+4
Will be used to check store attributes without actually performing the store. Needed to AMO bug fix.
2022-04-12Move real_time_clint into cfg_tRupert Swarbrick3-5/+8
2022-04-12Move varch into cfg_tRupert Swarbrick3-3/+6
2022-04-12Remove nprocs from cfg_tRupert Swarbrick2-5/+3
Now we have hartids, we can remove nprocs so that we have a single source of truth.
2022-04-12Move hartids into cfg_tRupert Swarbrick3-7/+11
The only slightly difficult thing here is that hartids will always be considered "overridden" by the time we get to sim_t::sim_t (either overridden by a command line argument, or overridden when we set default hartids just before the constructor). To allow downstream code to distinguish between "I picked IDs 0, 1, 2, 3 because the user asked for 4 processors" and "The user explicitly asked for IDs 0, 1, 2, 3", we have an extra explicit_hartids field.
2022-04-12Move the "default hartids" logic from sim.cc into spike.ccRupert Swarbrick1-10/+3
This moves another part of the "configuration" out of the generic sim.cc code.
2022-04-12Move start_pc into cfg_tRupert Swarbrick3-5/+5
2022-04-12Fix debug messages about invalid pmpregions/mmu-typesRupert Swarbrick1-2/+2
This was using the number of CPUs in total, rather than the CPU whose PMP regions / MMU type it was actually parsing.
2022-04-11Change processor_t to hold a pointer to an isa_parser_t (#973)Rupert Swarbrick3-17/+17
Before, it had another copy, which is a little unnecessary.
2022-04-11Split mem layout computation in spike.cc (#957)Rupert Swarbrick1-2/+29
The motivation here is mostly to enable a refactoring where the memory layout (sans allocated memory) gets passed to DTS/DTB code before we ever allocate anything. But it turns out to make merge_overlapping_memory_regions a bit simpler, which is an added bonus.
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson10-229/+389
Refactor trigger code
2022-04-11Fix hgatp CSR writeAnup Patel1-1/+1
The write mask is incorrectly computed by hgatp_csr_t::unlogged_write() which leads to hgatp.PPN bits not getting updated upon hgatp CSR write. This patch fixes hgatp CSR writes and gets KVM RISC-V working again on Spike. Fixes: 70b7e9ca2d04 ("mmu: support asid/vmid (#928)") Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-11Merge pull request #968 from 4vtomat/masterAndrew Waterman1-84/+20
[NFC] Clean up the redundant code by defining macros
2022-04-10Adjust the access index of vs2 to zero in vmv_x_s.h (#969)Brandon Wu1-21/+17
2022-04-09Replaced vector loop compare body with newly defined macro4vtomat1-90/+11
This commit uses new macro to replace loop compare body to enhance code reuse.
2022-04-09Adding new macro to replace repetitive code4vtomat1-0/+15
2022-04-07Merge pull request #966 from riscv-software-src/fix-riscv-buildAndrew Waterman9-11/+11
Rename processor_t::set_csr to put_csr to fix build on RISC-V
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman9-11/+11
The alternative would be to #undef set_csr after including encoding.h, but this solution strikes me as cleaner. Part of the reason is that set_csr was not a great name: it sounds like it implements the CSRRS (read & set) instruction, rather than impelementing a simple write.
2022-04-07Pass ref instead of pointer to trigger_updated()Tim Newsome3-5/+5
2022-04-07Add const to pointers where possible.Tim Newsome2-27/+27
2022-04-07Add module_t::~module_t()Tim Newsome2-0/+9
Also add virtual destructor trigger_t.
2022-04-06mmu: support asid/vmid (#928)Chih-Min Chao3-3/+13
The change makes [v]satp.asid and hgatp.vmid writtable and supports maximum length for rv32 and rv64. Software could write and read the satp.asid to get the valid length or check if the core supports asid/vmid or not. However, there is no official way to describe this hardware capability (device tree or something else). Two implementation flags are also added for future use and enabled by default. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2022-04-05Merge pull request #960 from marcfedorow/upstreamAndrew Waterman3-6/+15
Change misa CSR in associate with priv spec.
2022-04-05Make triggers a vector of trigger_t.Tim Newsome3-3/+3
Not just mcontrol_t.
generated by cgit v1.1 at 2024-10-20 01:17:39 +0000