riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-02-27	Add debug module authentication.	Tim Newsome	1	-2/+3
2018-02-01	Add --debug-sba option	Tim Newsome	1	-2/+3
2018-01-18	Support debug system bus access.	Tim Newsome	1	-4/+3
2017-12-11	Make progbuf a run-time option.	Tim Newsome	1	-2/+4
2017-11-15	Merge pull request #156 from p12nGH/noncontiguous_harts	Andrew Waterman	1	-3/+14
2017-11-15	Support for non-contiguous hartids	Gleb Gagarin	1	-3/+14
2017-11-03	Put HTIF in the device tree	Palmer Dabbelt	1	-0/+3
2017-06-14	Support 64-bit start PCs in reset vector.	Tim Newsome	1	-12/+10
2017-05-16	Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10	Palmer Dabbelt	1	-6/+6
2017-05-01	Fix segfault when accessing bad memory addresses	Andrew Waterman	1	-2/+3
2017-05-01	Set default entry point from ELF	Andrew Waterman	1	-2/+6
2017-04-30	Add option to set start pc	Andrew Waterman	1	-8/+18
2017-04-30	Support more flexible main memory allocation	Andrew Waterman	1	-24/+21
2017-04-17	Merge remote-tracking branch 'origin/priv-1.10' into HEAD	Megan Wachs	1	-48/+156
2017-03-30	fdt: move interrupt controller into its own node	Wesley W. Terpstra	1	-4/+7
2017-03-24	Default to 2 GiB of memory	Andrew Waterman	1	-1/+1
2017-03-22	riscv: replace rtc device with a real clint implementation	Wesley W. Terpstra	1	-13/+11
2017-03-21	sim: declare cores as interrupt-controllers for clint	Wesley W. Terpstra	1	-0/+2
2017-03-21	bootrom: set a0 to hartid and a1 to dtb before boot	Wesley W. Terpstra	1	-7/+7
2017-03-21	configstring: rename variables to dts	Wesley W. Terpstra	1	-4/+4
2017-03-21	bootrom: include compiled dtb	Wesley W. Terpstra	1	-1/+87
2017-03-21	sim: create DTS instead of config string	Wesley W. Terpstra	1	-26/+45
2017-02-13	Abstract register read mostly working.	Tim Newsome	1	-1/+1
2017-02-10	Implement hartstatus field.	Tim Newsome	1	-1/+1
2017-02-03	OpenOCD connects, and sends some data that we receive.	Tim Newsome	1	-4/+4
2016-12-16	Use correct format codes for reg_t and size_t	Stefan O'Rear	1	-2/+2
2016-08-29	Fix indent.	Tim Newsome	1	-1/+1
2016-06-22	Remove legacy HTIF; implement HTIF directly	Andrew Waterman	1	-14/+39
2016-05-23	Make -H halt the core right out of reset.	Tim Newsome	1	-3/+1
2016-05-23	Have Debug memory kind of working again.	Tim Newsome	1	-7/+2
2016-05-23	Add debug_module bus device.	Tim Newsome	1	-7/+8
2016-05-23	Make sure to translate Debug RAM addresses also.	Tim Newsome	1	-2/+3
2016-05-23	Can jump to and execute Debug ROM.	Tim Newsome	1	-1/+8
2016-05-23	Gutting direct-access gdb.	Tim Newsome	1	-1/+1
2016-05-23	Add --gdb-port	Tim Newsome	1	-1/+1
2016-05-23	Flush icache when using swbps and report to gdb.	Tim Newsome	1	-1/+1
2016-05-23	Add -H to start halted.	Tim Newsome	1	-2/+4
2016-05-23	Listen on a socket for gdb to connect to.	Tim Newsome	1	-0/+3
2016-05-02	Add back IPI support	Andrew Waterman	1	-7/+11
2016-05-02	Remove tohost/fromhost registers	Andrew Waterman	1	-7/+0
2016-04-30	Remove SCRs; add padding after config string	Andrew Waterman	1	-22/+15
2016-04-29	Move much closer to new platform-M memory map	Andrew Waterman	1	-18/+22
2016-04-28	Remove MTIME[CMP]; add RTC device	Andrew Waterman	1	-3/+12
2016-03-02	Use RV config string rather than FDT	Andrew Waterman	1	-37/+39
2016-03-02	New definitions of misa/marchid/mvendorid	Andrew Waterman	1	-1/+1
2016-03-02	Set default RV32 RAM size to 4 GiB - 256 MiB	Andrew Waterman	1	-2/+2
2015-11-12	Generate device tree for target machine	Andrew Waterman	1	-8/+47
2015-09-24	Refactor memory access code; add MMIO support	Andrew Waterman	1	-0/+9
2015-08-06	Add an option (-l) to display a log of execution in non-interactive mode.	Prashanth Mundkur	1	-0/+7
2015-05-31	Use single, shared real-time counter	Andrew Waterman	1	-2/+4