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AgeCommit message (Collapse)AuthorFilesLines
2018-01-18Support debug system bus access.Tim Newsome1-4/+3
2017-12-11Make progbuf a run-time option.Tim Newsome1-2/+4
Also add an implicit ebreak after the program buffer. This is not part of the spec, but hopefully it will be.
2017-11-15Merge pull request #156 from p12nGH/noncontiguous_hartsAndrew Waterman1-3/+14
Support for non-contiguous hartids
2017-11-15Support for non-contiguous hartidsGleb Gagarin1-3/+14
2017-11-03Put HTIF in the device treePalmer Dabbelt1-0/+3
I wanted to actually put the address of the HTIF into the DTS, but that seems to be a bit too much work: since the HTIF addresses are just defined in an ELF file it's a bit awkward to make that work. Instead, I'm just putting a dummy HTIF key in the DTS.
2017-06-14Support 64-bit start PCs in reset vector.Tim Newsome1-12/+10
2017-05-16Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10Palmer Dabbelt1-6/+6
2017-05-01Fix segfault when accessing bad memory addressesAndrew Waterman1-2/+3
2017-05-01Set default entry point from ELFAndrew Waterman1-2/+6
2017-04-30Add option to set start pcAndrew Waterman1-8/+18
2017-04-30Support more flexible main memory allocationAndrew Waterman1-24/+21
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-48/+156
2017-03-30fdt: move interrupt controller into its own nodeWesley W. Terpstra1-4/+7
2017-03-24Default to 2 GiB of memoryAndrew Waterman1-1/+1
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-13/+11
2017-03-21sim: declare cores as interrupt-controllers for clintWesley W. Terpstra1-0/+2
2017-03-21bootrom: set a0 to hartid and a1 to dtb before bootWesley W. Terpstra1-7/+7
2017-03-21configstring: rename variables to dtsWesley W. Terpstra1-4/+4
2017-03-21bootrom: include compiled dtbWesley W. Terpstra1-1/+87
2017-03-21sim: create DTS instead of config stringWesley W. Terpstra1-26/+45
2017-02-13Abstract register read mostly working.Tim Newsome1-1/+1
Fails with not supported for 128-bit. Fails with exception (on rv32) with 64-bit. Succeeds (on rv32) with 32-bit.
2017-02-10Implement hartstatus field.Tim Newsome1-1/+1
2017-02-03OpenOCD connects, and sends some data that we receive.Tim Newsome1-4/+4
2016-12-16Use correct format codes for reg_t and size_tStefan O'Rear1-2/+2
Fixes 32-bit build.
2016-08-29Fix indent.Tim Newsome1-1/+1
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-14/+39
2016-05-23Make -H halt the core right out of reset.Tim Newsome1-3/+1
Added a test, too.
2016-05-23Have Debug memory kind of working again.Tim Newsome1-7/+2
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
2016-05-23Add debug_module bus device.Tim Newsome1-7/+8
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
2016-05-23Make sure to translate Debug RAM addresses also.Tim Newsome1-2/+3
2016-05-23Can jump to and execute Debug ROM.Tim Newsome1-1/+8
Connect with gdb, and the core will jump to Debug ROM and start executing it. Then it crashes when it jumps to 0x400 because Debug RAM isn't implemented (and doesn't live there anyway, for now).
2016-05-23Gutting direct-access gdb.Tim Newsome1-1/+1
2016-05-23Add --gdb-portTim Newsome1-1/+1
It's necessary to be able to run multiple spikes at once on the same box.
2016-05-23Flush icache when using swbps and report to gdb.Tim Newsome1-1/+1
2016-05-23Add -H to start halted.Tim Newsome1-2/+4
2016-05-23Listen on a socket for gdb to connect to.Tim Newsome1-0/+3
So far it just listens, and gdb times out because it's not getting any messages back. Receive packets and verify their checksum.
2016-05-02Add back IPI supportAndrew Waterman1-7/+11
2016-05-02Remove tohost/fromhost registersAndrew Waterman1-7/+0
2016-04-30Remove SCRs; add padding after config stringAndrew Waterman1-22/+15
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-18/+22
Reset vector is at 0x1000; below that is reserved for debug Memory is at 0x80000000
2016-04-28Remove MTIME[CMP]; add RTC deviceAndrew Waterman1-3/+12
2016-03-02Use RV config string rather than FDTAndrew Waterman1-37/+39
2016-03-02New definitions of misa/marchid/mvendoridAndrew Waterman1-1/+1
2016-03-02Set default RV32 RAM size to 4 GiB - 256 MiBAndrew Waterman1-2/+2
This allows, by default, 256 MiB of addressable I/O space.
2015-11-12Generate device tree for target machineAndrew Waterman1-8/+47
2015-09-24Refactor memory access code; add MMIO supportAndrew Waterman1-0/+9
Of course, it doesn't do anything yet.
2015-08-06Add an option (-l) to display a log of execution in non-interactive mode.Prashanth Mundkur1-0/+7
Interactive (-d) mode overrides this option when both are specified.
2015-05-31Use single, shared real-time counterAndrew Waterman1-2/+4
This required disentangling INSTRET/CYCLE from TIME.
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-9/+4
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha
2014-08-15Added PC histogram option.Christopher Celio1-1/+12
- Spits out all PCs (on 4B granularity) executed with count. - Requires a compile time configuration option. - Also requires a run-time flag.