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AgeCommit message (Expand)AuthorFilesLines
2022-03-17Inline trap_t methods so they can be used in fesvr codeAndrew Waterman1-1/+0
2022-02-18Remove disasm.cc/disasm.h from riscv subproject (#919)Rupert Swarbrick1-2/+0
2022-01-30add instructions function for cmoliweiwei1-0/+7
2021-12-27Update instruction vmandnot.mm, vmornot.mm -> vmandn.mm, vmorn.mm (#896)Yueh-Ting (eop) Chen1-2/+2
2021-11-02Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)Markku-Juhani O. Saarinen1-4/+4
2021-10-14Split 'P' to EXT_ZPN and friends (#830)marcfedorow1-14/+1
2021-09-08Extract csr_t implementations to separate fileScott Johnson1-0/+1
2021-09-08Extract CSR class hierarchy to new fileScott Johnson1-0/+1
2021-08-09rvv fix 2021-08-09 (#768)Chih-Min Chao1-5/+10
2021-08-08Removed SWAP16 encoding and implementation header. (#766)marcfedorow1-1/+0
2021-07-28Significantly speed up compilation with GCCAndrew Waterman1-2/+0
2021-07-20Priv virtual memory updates (#750)Daniel Lustig1-0/+7
2021-06-04rvv: vdot has been removedChih-Min Chao1-3/+0
2021-06-02Remove Duff's Device in main simulation loop (#721)Andrew Waterman1-7/+0
2021-05-10Support RISC-V p-ext-proposal v0.9.2 (#637)ChunPing Chung1-0/+345
2021-03-08Merge pull request #649 from ben-marshall/scalar-crypto-fixAndrew Waterman1-4/+8
2021-02-24rvv: add vsetivliChih-Min Chao1-0/+1
2021-02-24rvv: add vse1/vle1Chih-Min Chao1-0/+2
2021-02-23rvv: rename sqrt/reciprocal instructionsChih-Min Chao1-2/+2
2021-02-18scalar-crypto: Fix decoding of RV64 AES instructions.Ben Marshall1-4/+8
2021-02-04Refactor headersAndrew Waterman1-0/+1
2021-01-22scalar-crypto: Initial spike support for v0.8.1 (#635)Ben Marshall1-0/+29
2021-01-17rvb: add xperm.[nbhw] (#629)Chih-Min Chao1-0/+4
2021-01-08Update Zba/Zbb/Zbc to v0.93; Zbs/Zbe to v0.94-draftAndrew Waterman1-32/+19
2020-12-02rvv: index load/store have benn separated into ordered and unordered parts (#...Chih-Min Chao1-8/+12
2020-10-22Remove subu.w; change addu.w definitionAndrew Waterman1-1/+0
2020-10-22[riscv-bitmanip] Add sh[123]add[u.w] instructionClifford Wolf1-0/+6
2020-10-22[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.92Clifford Wolf1-0/+5
2020-10-22[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.91Clifford Wolf1-0/+6
2020-10-22[riscv-bitmanip] Add bitmanip instructionsClifford Wolf1-0/+92
2020-09-22Separate build of spike and spike-dasmAndrew Waterman1-1/+0
2020-08-31rvv: add reciprocal instructionsChih-Min Chao1-0/+2
2020-08-27rvv: remove quad instructionsChih-Min Chao1-7/+0
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao1-0/+1
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao1-1/+19
2020-07-29rvv: op: fix amo namingChih-Min Chao1-36/+36
2020-07-09Implement new instructions of hypervisor extensionAnup Patel1-0/+18
2020-06-16zfh: implement all instructionsChih-Min Chao1-1/+40
2020-06-10ext: build libriscv PIC to make it linkable to ext libraryChih-Min Chao1-0/+2
2020-05-28rvv: add new explicit eew load/store instructionsChih-Min Chao1-44/+32
2020-05-28rvv: add amo instructionsChih-Min Chao1-0/+39
2020-05-28rvv: add new singed/unsiged extension instructionsChih-Min Chao1-0/+6
2020-04-26fdt: import fdt library from OpenSBIChih-Min Chao1-0/+1
2020-04-24rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+2
2020-04-20rvv: add float conversion for rtz variantsChih-Min Chao1-0/+6
2020-01-13rvv: add vmv[1248]r.vChih-Min Chao1-0/+4
2019-12-20rvv: add unsigned averageChih-Min Chao1-0/+4
2019-12-20rvv: replace vn suffic by 'w'Chih-Min Chao1-12/+12
2019-12-20rvv: add load/store whole register instructionsChih-Min Chao1-0/+2
2019-12-20rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-5/+6
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