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2023-04-14Add support for new instructions of Zvfbfwma extensionWeiwei Li1-0/+5
2023-04-14Add support for new instructions of Zvfbfmin extensionWeiwei Li1-0/+5
2023-04-14Add support for new instructions of Zfbfmin extensionWeiwei Li1-2/+10
2023-04-12Add debug_defines.h to list of installed headersJerry Zhao1-0/+1
2023-04-03Implement Zfa.Philipp Tomsich1-0/+45
This passes our developer test suite, when comparing output (signature) against the SAIL implementation. If any corner-cases require additional changes after ACT goes upstream, we can apply an add-on patch.
2023-03-20Implement Smrnmi extensionAndrew Waterman1-0/+4
We don't model any sources of RNMI, so this is mostly vestigial.
2023-02-04Add disasm/extension/rocc.h to installed headersJerry Zhao1-0/+3
2023-01-31Zicond: implement Zicond (conditional integer operations)Philipp Tomsich1-0/+5
This implements the Zicond (conditional integer operations) extension, as of version 1.0-draft-20230120. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf for the proposed specification and usage details.
2022-12-22Remove non-installed header lists from Makefile fragmentsAndrew Waterman1-34/+0
It's just dead code. (Dependences on headers are auto-generated as `.d` files.)
2022-12-20Reduce compile time increase introduced by #1189Andrew Waterman1-13/+4
Generate one object file per instruction rather than two, which reduces the overhead of invoking the compiler so many times. This also reduces the size of the (unstripped) binary substantially.
2022-12-20Add logged variants of insn templatesJerry Zhao1-5/+13
2022-12-16Add missing vector_unit.h to install headers listJerry Zhao1-1/+2
2022-12-16Add missing abstract_interrupt_controller.h to header listsJerry Zhao1-0/+2
2022-12-15Don't install instruction decode macrosJerry Zhao1-3/+1
2022-12-15Merge pull request #1180 from ucb-bar/cleancfgAndrew Waterman1-0/+1
Pull mmu.h out of cfg.h
2022-12-15Add cfg.cc to hold internal implementation of mem_cfg_tJerry Zhao1-0/+1
2022-12-15Split decode.h into public decode.h and private decode_macros.hJerry Zhao1-0/+1
* decode.h contains constants/typedefs/classes. This should not depend on config.h * decode_macros.h contains internally used macros, and depends on config.h
2022-12-13Move boost asio socket interface to socketif_tJerry Zhao1-1/+3
This reduces dependencies on config.h in sim.h
2022-12-12Pull vector unit into separate source/headerJerry Zhao1-0/+2
2022-11-17add support for zcmtWeiwei Li1-0/+4
add suport for jvt: Table entries follow the current data endianness
2022-11-17add support for zcmpWeiwei Li1-0/+9
2022-11-17add support for zcbWeiwei Li1-1/+19
2022-10-17Merge branch 'master' into plic_uart_v1plic_uart_v1Andrew Waterman1-1/+34
2022-09-23Build and install lib and header dependencies for HammerJerin Joy1-1/+31
https://github.com/rivosinc/hammer Signed-off-by: Jerin Joy <joy@rivosinc.com>
2022-05-16Include recently added headers in riscv/riscv.mk.inPirmin Vogel1-0/+3
2022-04-20Add ns16550 serial device emulationAnup Patel1-0/+1
The ns16550 is a widely use serial device so we add a simplified ns16550 device emulation which is good enough for Linux, OpenSBI, and hypervisors to use as console. Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-20Add PLIC emulationAnup Patel1-0/+1
We need an interrupt controller in Spike which will allow us to emulate more real-world devices such as UART, VirtIO net, VirtIO block, etc. The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt controller in existing RISC-V platforms so this patch adds PLIC emulation for Spike. Signed-off-by: Anup Patel <anup@brainfault.org>
2022-03-30Create triggers.cc, triggers.h.Tim Newsome1-0/+2
2022-03-29Split isa_parser_t out of processor.* and into its own file (#955)Rupert Swarbrick1-0/+1
The main motivation for this is that we want to move the ISA parsing logic to run before we even construct a simulator. That's probably a bit nicer if we don't depend on the processor header. It also means that we can stop depending on processor.h in disasm.cc or spike_log_parser.cc (both through disasm.h), which feels a bit cleaner: making sense of an instruction trace shouldn't really require knowledge of the internal state of a processor.
2022-03-18Initial step towards factoring out command line configurationRupert Swarbrick1-0/+1
This commit defines a "cfg_t" structure, which currently just holds the initrd address range. It will be augmented in future commits to hold other configuration arguments as well. To represent a configuration argument, we define an arg_t base class. This holds a current value, together with a flag that tells us whether the value has been updated from the default. The idea is that in future we're going to use that flag when reading a DTB file: if an argument has actually been specified on the command line, we need to take it into account; if not, we can ignore the default and use the DTB file's supplied value.
2022-03-17Inline trap_t methods so they can be used in fesvr codeAndrew Waterman1-1/+0
2022-02-18Remove disasm.cc/disasm.h from riscv subproject (#919)Rupert Swarbrick1-2/+0
These also appear in the disasm subproject (where they make more sense), which generates Make warnings about duplicate rules. Before this commit, we were including the code in both libriscv.a and libdisasm.a: $ git rev-parse HEAD c2f30c33304c96917bdb0ab7e2d4d6a2d71d1d25 $ nm libriscv.a | c++filt | grep ' T ' | grep disassemble nm: libsoftfloat.a: file format not recognized nm: libfdt.a: file format not recognized 0000000000010b00 T disassembler_t::add_instructions(isa_parser_t*) 00000000000070c0 T disassembler_t::add_insn(disasm_insn_t*) 000000000001be00 T disassembler_t::disassembler_t(isa_parser_t*) 000000000001be00 T disassembler_t::disassembler_t(isa_parser_t*) 0000000000003d30 T disassembler_t::~disassembler_t() 0000000000003d30 T disassembler_t::~disassembler_t() 0000000000003ae0 T disassembler_t::probe_once(insn_t, unsigned long) const 0000000000003cb0 T disassembler_t::disassemble[abi:cxx11](insn_t) const 0000000000003bb0 T disassembler_t::lookup(insn_t) const $ nm libdisasm.a | c++filt | grep ' T ' 0000000000010b00 T disassembler_t::add_instructions(isa_parser_t*) 00000000000070c0 T disassembler_t::add_insn(disasm_insn_t*) 000000000001be00 T disassembler_t::disassembler_t(isa_parser_t*) 000000000001be00 T disassembler_t::disassembler_t(isa_parser_t*) 0000000000003d30 T disassembler_t::~disassembler_t() 0000000000003d30 T disassembler_t::~disassembler_t() 0000000000003ae0 T disassembler_t::probe_once(insn_t, unsigned long) const 0000000000003cb0 T disassembler_t::disassemble[abi:cxx11](insn_t) const 0000000000003bb0 T disassembler_t::lookup(insn_t) const 0000000000000000 T csr_name(int) Note that this change will have no effect on the contents of libspike_main.a or libspike_dasm.a: both of these include libriscv.a and libdisasm.a.
2022-01-30add instructions function for cmoliweiwei1-0/+7
prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
2021-12-27Update instruction vmandnot.mm, vmornot.mm -> vmandn.mm, vmorn.mm (#896)Yueh-Ting (eop) Chen1-2/+2
Refer to rvv-spec v1.0-rc2
2021-11-02Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)Markku-Juhani O. Saarinen1-4/+4
Krypto 1.0 changes: Entropy source CSR, name. List scalar crypto instruction groupings, as there is no single K extension. Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
2021-10-14Split 'P' to EXT_ZPN and friends (#830)marcfedorow1-14/+1
* Added ZMMUL extension * Splitted P-ext to its zeds * Typo fix
2021-09-08Extract csr_t implementations to separate fileScott Johnson1-0/+1
This will enable me to use some forward references here soon.
2021-09-08Extract CSR class hierarchy to new fileScott Johnson1-0/+1
2021-08-09rvv fix 2021-08-09 (#768)Chih-Min Chao1-5/+10
* rvv: vmadc/vmsbc have been separated into carry and no-carry versions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: rename file name by opcode name change Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-08-08Removed SWAP16 encoding and implementation header. (#766)marcfedorow1-1/+0
SWAP16 is an alias to PKBT16 since p-spec v0.9.3.
2021-07-28Significantly speed up compilation with GCCAndrew Waterman1-2/+0
Precompiled headers were broken because they weren't compiled with the same -fPIC setting as the rest of the code. Fix by just making everything use -fPIC.
2021-07-20Priv virtual memory updates (#750)Daniel Lustig1-0/+7
* Priv virtual memory updates * Priv 1.12 requires page faults when the address translation process reaches a PTE with any reserved bit set * Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since Spike is sequentially consistent and does not model PMAs) * Add Svinval instructions Even though I updated riscv-opcodes separately, I merged the new defines into riscv/encoding.h manually, because riscv-opcodes seems to be a step ahead of riscv-isa-sim for a few vector opcodes, causing conflicts when regenerating encoding.h... If that gets fixed, and encoding.h gets regenerated automatically, I can remove it from this PR to avoid conflicts. * Svinval: use #include rather than copying code ..for the Svinval functions that are implemented in ways that just mimic SFENCE/HFENCE instructions Thanks to @aswaterman for the suggestion
2021-06-04rvv: vdot has been removedChih-Min Chao1-3/+0
They have been remove in 0.10 spec Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-06-02Remove Duff's Device in main simulation loop (#721)Andrew Waterman1-7/+0
With recent compilers on recent computers, the much simpler version of the code is actually slightly faster. I suspect, but haven't proven, that more accurate indirect jump prediction is the main explanation. Reduced I$ pressure might be a secondary factor.
2021-05-10Support RISC-V p-ext-proposal v0.9.2 (#637)ChunPing Chung1-0/+345
* rvp: add 8/16 bits add/sub simd instructions * rvp: add 8/16 bits shift simd instructions * rvp: add 8/16 bits compare simd instructions * rvp: add 8/16 bits multiply simd instructions * rvp: add 8/16 bits misc simd instructions * rvp: add 8 bits unpacking simd instructions * rvp: update suppported extention and add restriction * rvp: update encoding.h and riscv.mk.in * rvp: disasm: add simd instruction support * rvp: update readme for p-ext simd instructions * rvp: fix rvp support version * rvp: update encoding.h generated from riscv-opcode p-ext branch * rvp: rename some macro argument * rvp: add pk[bb,bt,tt,tb][16,32] instructions * rvp: add kadd32, [su]maqa[_su] instructions * rvp: fix missing initial value of pd * rvp: add msw 32x32 multiply & add instructions * rvp: change to use extract64 * rvp: add msw 32x16 multiply & add instructions * rvp: fix some style * rvp: change reduction marcro definition * rvp: add signed 16x32 add/subtract instructions * rvp: use stdint to replace hardcode max/minimum * rvp: refactor some p-ext macro code * rvp: add partial simd miscellaneous instructions * rvp: add signed 16 x 64 add/subtract Instructions * rvp: add 64-bit add & sub instructions * rvp: add 32-bit mul with 64-bit add/sub instructions * rvp: add 16-bit mul with 64-bit add/sub instructions * rvp: disasm: add 64 bit profile instruction support * rvp: add Q15 saturation instructions * rvp: fix kmar64/kmsr64 saturation behavior * rvp: add 32-bit computation instructions * rvp: add rdov/clrov and fix khm16 behavior of setting OV flag * rvp: add non simd miscellaneous instructions * rvp: add Q31 saturation instructions * rvp: disasm: add non-simd instruction support * rvp: add 32 bits add/sub simd instructions * rvp: fix left shift saturation bug * rvp: add 32 bits shift simd instructions * rvp: add rv64 only Q15 simd instructions * rvp: add rv64 only 32-bit multiply instructions * rvp: add rv64 only 32-bit miscellaneous instructions * rvp: add rv64 only 32-bit mul & add instructions * rvp: add rv64 only 32-bit parallel mul & add instructions * rvp: add rv64 only non-simd 32-bit shift instructions * rvp: disasm: remove redundant tab * rvp: disasm: add rv64 only instructions support * rvp: change ov csr to ucode to match v0.5.2 spec * rvp: update readme for p-ext 0.5.2 * rvp: update to p-ext v0.9.1 * rvp: update to p-ext v0.9.2 * rvp: update readme for p-ext 0.9.2 * rvp: fix macro for PKxx16 & PKxx32 commands. * rvp: fix missing for in PKxxdd macro * Sign-extension for p-ext insns * * Fixed uclipNN insns while sh >> 64 is an UB. * Added missing OV * Added missing sext_xlen * Remove unused macroses * Sign extension for RD_PAIR macro * rvp: remove lost tab Co-authored-by: Mark Fedorov <mark.fedorov@cloudbear.ru>
2021-03-08Merge pull request #649 from ben-marshall/scalar-crypto-fixAndrew Waterman1-4/+8
Scalar crypto fixes
2021-02-24rvv: add vsetivliChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-24rvv: add vse1/vle1Chih-Min Chao1-0/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-23rvv: rename sqrt/reciprocal instructionsChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-18scalar-crypto: Fix decoding of RV64 AES instructions.Ben Marshall1-4/+8
Historically, one could uniquely decode any RISC-V instruction based on the instruciton to decode, plus a MATCH and MASK pair. The scalar crypto extension adds instructions for accelerating the AES algorithm which work very differently on RV32 and RV64. However, they overlap in terms of opcodes. The instructions are always mutually exclusive, and so it makes sense to overlap them this way to save encoding space. This exposed a problem, where previously Spike assumed the decoder function was something like: > decode(instr_word, MATCH, MASK) Now it needed to be > decode(instr_word, MATCH, MASK, current_xlen) To get around this in the initial implementation, the instructions which shared opcodes were implemented in the same *.h file - e.g. aesds.h contained an implementation of aes32dsi, and aes64ds. We detected xlen in the file, and executed the appropriate instruction logic. This worked fine for our limited set of benchmarks. After more extensive testing, we found that Spike has an optimisation which changes the order in which it tries to decode instructions based on past instructions. Running more extensive tests exposed the fact that the decoding logic could still not unambiguously decode the instructions. Hence, more substantial changes were needed to tell spike that an instruction is RV32 or RV64 only. These changes have been implemented as part of - riscv/encoding.h - disasm/disasm.cc - riscv/processor.cc/h Basically, every instr_desc_t has an extra field which marks which base architecture the instruction can be exectuted on. This bitfield can be altered for particular instructions. The changes to riscv/insns/* simply split out the previously combined instructions into a separate header files. On branch scalar-crypto-fix Changes to be committed: modified: disasm/disasm.cc modified: riscv/encoding.h new file: riscv/insns/aes32dsi.h new file: riscv/insns/aes32dsmi.h new file: riscv/insns/aes32esi.h new file: riscv/insns/aes32esmi.h new file: riscv/insns/aes64ds.h new file: riscv/insns/aes64dsm.h new file: riscv/insns/aes64es.h new file: riscv/insns/aes64esm.h deleted: riscv/insns/aesds.h deleted: riscv/insns/aesdsm.h deleted: riscv/insns/aeses.h deleted: riscv/insns/aesesm.h modified: riscv/processor.cc modified: riscv/processor.h modified: riscv/riscv.mk.in
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