riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-02-04	Refactor headers	Andrew Waterman	1	-0/+1
2021-01-22	scalar-crypto: Initial spike support for v0.8.1 (#635)	Ben Marshall	1	-0/+29
2021-01-17	rvb: add xperm.[nbhw] (#629)	Chih-Min Chao	1	-0/+4
2021-01-08	Update Zba/Zbb/Zbc to v0.93; Zbs/Zbe to v0.94-draft	Andrew Waterman	1	-32/+19
2020-12-02	rvv: index load/store have benn separated into ordered and unordered parts (#...	Chih-Min Chao	1	-8/+12
2020-10-22	Remove subu.w; change addu.w definition	Andrew Waterman	1	-1/+0
2020-10-22	[riscv-bitmanip] Add sh[123]add[u.w] instruction	Clifford Wolf	1	-0/+6
2020-10-22	[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.92	Clifford Wolf	1	-0/+5
2020-10-22	[riscv-bitmanip] Changes for RISC-V Bitmanip Spec 0.91	Clifford Wolf	1	-0/+6
2020-10-22	[riscv-bitmanip] Add bitmanip instructions	Clifford Wolf	1	-0/+92
2020-09-22	Separate build of spike and spike-dasm	Andrew Waterman	1	-1/+0
2020-08-31	rvv: add reciprocal instructions	Chih-Min Chao	1	-0/+2
2020-08-27	rvv: remove quad instructions	Chih-Min Chao	1	-7/+0
2020-07-29	rvv: add vrgatherei16.vv	Chih-Min Chao	1	-0/+1
2020-07-29	rvv: add new whole reg load/store instructions	Chih-Min Chao	1	-1/+19
2020-07-29	rvv: op: fix amo naming	Chih-Min Chao	1	-36/+36
2020-07-09	Implement new instructions of hypervisor extension	Anup Patel	1	-0/+18
2020-06-16	zfh: implement all instructions	Chih-Min Chao	1	-1/+40
2020-06-10	ext: build libriscv PIC to make it linkable to ext library	Chih-Min Chao	1	-0/+2
2020-05-28	rvv: add new explicit eew load/store instructions	Chih-Min Chao	1	-44/+32
2020-05-28	rvv: add amo instructions	Chih-Min Chao	1	-0/+39
2020-05-28	rvv: add new singed/unsiged extension instructions	Chih-Min Chao	1	-0/+6
2020-04-26	fdt: import fdt library from OpenSBI	Chih-Min Chao	1	-0/+1
2020-04-24	rvv: add vfslide1[down\|up].vf and refine checking rule	Chih-Min Chao	1	-0/+2
2020-04-20	rvv: add float conversion for rtz variants	Chih-Min Chao	1	-0/+6
2020-01-13	rvv: add vmv[1248]r.v	Chih-Min Chao	1	-0/+4
2019-12-20	rvv: add unsigned average	Chih-Min Chao	1	-0/+4
2019-12-20	rvv: replace vn suffic by 'w'	Chih-Min Chao	1	-12/+12
2019-12-20	rvv: add load/store whole register instructions	Chih-Min Chao	1	-0/+2
2019-12-20	rvv: rename vfncvt suffix and add rod rouding type	Chih-Min Chao	1	-5/+6
2019-12-20	rvv: add vqm* 'Quad-Widening Integer Multiply-Add'	Chih-Min Chao	1	-0/+7
2019-12-20	rvv: add quad insn and new vlenb csr	Chih-Min Chao	1	-7/+0
2019-11-15	Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubu	Andrew Waterman	1	-1/+0
2019-11-11	rvv: fix vmv.x.s signed-ext issue	Chih-Min Chao	1	-1/+1
2019-10-29	rvv: remove vmford	Chih-Min Chao	1	-2/+0
2019-07-22	Implement MMIO device plugins.	Aaron Jones	1	-0/+3
2019-07-19	vext.x.v -> vmv.x.s; unary operation encoding changes	Andrew Waterman	1	-1/+1
2019-07-12	Remove old header from makefile	Andrew Waterman	1	-1/+0
2019-07-11	Fix support for 32-bit hosts (but no V extension in that case!)	Andrew Waterman	1	-1/+1
2019-07-05	vmfirst/vmpopc have been renamed to vfirst/vpopc	Andrew Waterman	1	-2/+2
2019-06-18	rvv: add floating-point instructions	Chih-Min Chao	1	-0/+96
2019-06-18	rvv: add load/store instructions	Chih-Min Chao	1	-0/+47
2019-06-18	rvv: add integer/fixed-point/mask/reduction/permutation instructions	Chih-Min Chao	1	-0/+206
2019-06-18	rvv: add control instructions and system register access	Chih-Min Chao	1	-0/+8
2019-06-09	rvv: re-arrange instruction list by different extension	Chih-Min Chao	1	-129/+155
2018-05-31	Put simif_t declaration in its own file. (#209)	Andy Wright	1	-0/+1
2018-05-18	Fix install of missed header. (#207)	Prashanth Mundkur	1	-0/+1
2018-05-18	Extract out device-tree generation and compilation into an exported api. (#197)	Prashanth Mundkur	1	-0/+2
2017-09-28	Implement Q extension	Andrew Waterman	1	-0/+32
2017-05-16	Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10	Palmer Dabbelt	1	-2/+4