riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2023-12-11	riscv: sim.cc: Parse for "sifive,plic-1.0.0" if "riscv,plic0" is absent	Tan En De	1	-1/+2
	"riscv,plic0" and "sifive,plic-1.0.0" in device tree's "compatible" string point to the same driver, as can be seen from drivers/irqchip/irq-sifive-plic.c in Linux kernel. https://github.com/torvalds/linux/commit/5873ba559101fa37ad9764e79856f71bf54021aa The other two "compatible" strings below isn't included, because of their different plic behavior (plic_edge_init instead of plic_init as explained in the Linux commit). - "andestech,nceplic100" - "thead,c900-plic" Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-12-08	Fix Spike --device option to pass on args to downstream plugins	joey0320	1	-1/+1

2023-06-20	device_t: Add device_factory_t's for ns16550/clint/plic	Jerry Zhao	1	-0/+37

2023-06-20	devices: Pass const pointers to sim_t to clint/plic	Jerry Zhao	1	-1/+1

2023-04-07	Implement pending bits for plic	Jiajie Chen	1	-1/+21

2023-03-09	Use simif_t instead of sim_t for clint/plic	Scott Johnson	1	-2/+2
	In keeping with the spirit of simif_t.
2023-03-01	Fix PLIC on big-endian hosts	Andrew Waterman	1	-3/+3

2023-03-01	Remove unnecessary conditional in plic_t::load	Andrew Waterman	1	-3/+1
	It's safe to overwrite bytes when returning false.
2023-03-01	Correctly instantiate PLIC contexts for mixed-hart targets	Andrew Waterman	1	-5/+8
	This commit started as an attempt to make the PLIC tolerant of discontiguous hart IDs, but it turns out it was already most of the way there: PLIC contexts can still be dense even if the hart IDs are not. Nevertheless, I wanted to avoid passing the procs vector directly to the plic_t constructor. In removing it, I realized I could also get rid of the smode parameter by querying whether each hart has S-mode. This is also more correct; previously, we were instantiating the PLIC as though all harts had S-mode, regardless of whether they actually did.
2023-03-01	Refactor plic_t and plic_context_t initialization	Andrew Waterman	1	-18/+5

2023-02-28	Remove unused plic_context_t::num field	Andrew Waterman	1	-1/+0

2023-02-28	Remove unused plic_t::procs field	Andrew Waterman	1	-1/+1

2023-02-22	optimize `num_ids_word` init logic;	Wade	1	-6/+3
	init `max_prio` by initialization-list
2023-02-18	fix unintentionally plic context update when `val > max_prio` and `offset == ↵	Wade	1	-3/+4
	CONTEXT_THRESHOLD`
2022-11-23	Make reserved PLIC behavior more realistic	Andrew Waterman	1	-22/+32
	Most implementations can't raise precise exceptions as a function of sub-page addressing, so don't attempt to do so here. Also, support double-word-sized writes. Although PLICs aren't required to support this behavior, they are allowed to. Some existing implementations support this behavior, and some existing software relies upon it (unfortunately).
2022-10-17	Make PLIC/NS16550 coding style more conformant	Andrew Waterman	1	-73/+55

2022-04-20	Add PLIC emulation	Anup Patel	1	-0/+393
	We need an interrupt controller in Spike which will allow us to emulate more real-world devices such as UART, VirtIO net, VirtIO block, etc. The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt controller in existing RISC-V platforms so this patch adds PLIC emulation for Spike. Signed-off-by: Anup Patel <anup@brainfault.org>