| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2013-08-11 | Instructions are no longer member functions | Andrew Waterman | 1 | -25/+2 |
| 2013-07-28 | Don't flush TLB on PTBR writes (only FATC) | Andrew Waterman | 1 | -1/+1 |
| 2013-07-26 | New supervisor mode | Andrew Waterman | 1 | -17/+3 |
| 2013-07-26 | Remove more vector stuff | Andrew Waterman | 1 | -3/+0 |
| 2013-07-26 | Rip out RVC for now | Andrew Waterman | 1 | -42/+17 |
| 2013-07-26 | Generate instruction decoder dynamically | Andrew Waterman | 1 | -22/+18 |
| 2013-03-29 | add load-reserved/store-conditional instructions | Andrew Waterman | 1 | -2/+13 |
| 2013-03-25 | add BSD license | Andrew Waterman | 1 | -0/+2 |
| 2013-03-25 | truncate effective addresses in rv32 | Andrew Waterman | 1 | -11/+4 |
| 2013-02-15 | don't store host pointers in soft TLB | Andrew Waterman | 1 | -15/+18 |
| 2013-02-13 | clean up fetch-execute loop a bit | Andrew Waterman | 1 | -28/+32 |
| 2013-02-13 | add I$/D$/L2$ simulators | Andrew Waterman | 1 | -15/+23 |
| 2012-01-24 | check that virtual addresses are sign-extended | Andrew Waterman | 1 | -0/+2 |
| 2012-01-22 | disentangle decode.h from other headers | Andrew Waterman | 1 | -0/+1 |
| 2011-11-01 | Fixed tight coupling of host and target page size | Andrew Waterman | 1 | -1/+1 |
| 2011-10-27 | changed page size to 8KB | Andrew Waterman | 1 | -4/+3 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+191 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -194/+0 |
| 2011-06-12 | [xcc] minor performance tweaks | Andrew Waterman | 1 | -4/+13 |
| 2011-06-11 | [xcc] tlb now stores host addresses | Andrew Waterman | 1 | -16/+16 |
| 2011-06-11 | [xcc] cleaned up mmu code | Andrew Waterman | 1 | -96/+26 |
| 2011-05-31 | [sim] fault on failed addr translations | Andrew Waterman | 1 | -1/+21 |
| 2011-05-31 | [sim] minor sim cleanup | Andrew Waterman | 1 | -16/+6 |
| 2011-05-29 | [sim,opcodes] improved sim build and run performance | Andrew Waterman | 1 | -50/+44 |
| 2011-05-28 | [fesvr,xcc,sim] fixed multicore sim for akaros | Andrew Waterman | 1 | -14/+23 |
| 2011-05-16 | [sim,pk] cleanups & initial virtual memory support | Andrew Waterman | 1 | -38/+46 |
| 2011-05-13 | [sim] initial support for virtual memory | Andrew Waterman | 1 | -17/+126 |
| 2011-05-06 | [sim] fixed building sim without cache simulators | Andrew Waterman | 1 | -1/+1 |
| 2011-04-30 | [sim] hacked in a dcache simulator | Andrew Waterman | 1 | -1/+33 |
| 2011-04-15 | [sim] added icache simulator (disabled by default) | Andrew Waterman | 1 | -0/+9 |
| 2011-04-12 | [sim,pk] fixed minor pk bugs and trap codes | Andrew Waterman | 1 | -3/+5 |
| 2011-04-11 | [xcc,sim,opcodes] more rvc instructions and bug fixes | Andrew Waterman | 1 | -3/+1 |
| 2011-04-09 | [xcc, sim] added rvc insn c.li; misc fixes | Andrew Waterman | 1 | -1/+4 |
| 2011-04-09 | [xcc,pk,sim,opcodes] added first RVC instruction | Andrew Waterman | 1 | -3/+8 |
| 2010-10-05 | [xcc,sim] eliminated vectored traps | Andrew Waterman | 1 | -2/+2 |
| 2010-09-10 | [sim, pk] cleaned up exception vectors and FP exc flags | Andrew Waterman | 1 | -7/+7 |
| 2010-07-28 | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 1 | -1/+1 |
| 2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+76 |
