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2023-08-14rename *envcfg.HADE to *envcfg.ADUEVed Shanbhogue1-2/+2
2023-07-13refactor: mcontrol/mcontrol6: extend check_triggers() with tval parameterYenHaoChen1-3/+3
2023-06-19mmu: support load/store longer than 64-bits.Gianluca Guida1-2/+15
2023-05-11Plumb in effective virtual bit to take_trigger_action()rbuchner1-8/+8
2023-05-11Add split_misaligned_access() to mem_access_info_trbuchner1-2/+2
2023-05-11Pass mem_access_info_t into walk()rbuchner1-3/+7
2023-05-11Use access_info within store_slow_path rather than xlate_flagsRyan Buchner1-1/+1
2023-05-11Use access_info.effective_virt when failed mmio_store (i.e. device detects ↵rbuchner1-1/+1
access fault) Fixes case 3 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
2023-05-11Adjust store_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner1-7/+9
2023-05-11Use access_info within load_slow_path rather than xlate_flagsRyan Buchner1-2/+2
Fixes case 2 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
2023-05-11Use access_info.effective_virt when failed mmio_load (i.e. device detects ↵rbuchner1-1/+1
access fault) Fixes case 3 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
2023-05-11Use access_info.effective_virt when access_fault due to non-reservable lrrbuchner1-1/+1
Fixes case 4 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
2023-05-11Adjust load_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner1-9/+11
2023-05-11Add structure (mem_access_info_t) for holding memory access informationRyan Buchner1-18/+10
Add complementary function for generating access information. Update mmu_t::translate() to accept a mem_access_info_t.
2023-05-11Add is_special_access() to xlate_flags_trbuchner1-4/+4
2023-05-11Add xlate_flags_t structrbuchner1-17/+17
Use xlate_flags_t rather than XLATE_FLAGS preprocessing directives
2023-05-11Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRTRyan Buchner1-3/+3
More readable/understandable.
2023-03-16Make MPRV logic consistent; factor it outAndrew Waterman1-2/+2
I believe the fact that mmu_t::refill_tlb was ignoring debug mode was benign, but certainly paying attention to debug mode is OK.
2023-03-04Don't issue misaligned or non-power-of-2 MMIO accessesScott Johnson1-7/+24
@aswaterman explains: Rather than requiring each MMIO device to support arbitrary sizes and alignments, decompose MMIO misaligned loads and stores in such a way as to guarantee their constituent parts are always aligned. (Specifically, they now always decompose to a sequence of one-byte accesses.) This is not a semantic change for main-memory accesses, but it is a semantic change for I/O devices. It makes them more realistic, in that most bus standards don't support non-power-of-2-sized accesses.
2023-01-27Use Svadu control bits to drive A/D updatesAaron Durbin1-2/+4
The Svadu (https://github.com/riscv/riscv-svadu) extension updates the A/D bits of PTEs: 1. In S/HS mode when menvcfg.hade=1 2. In G-stage page tables when menvcfg.hade=1 3. In VS mode when henvcfg.hade=1 To enable this behavior the 'svadu' ISA string is needed. This newly added behavior supplants the --mmu-dirty flag. However, that flag is not yet removed.
2023-01-04Respect --mmu-dirty flag instead of --enable-dirtyJerry Zhao1-16/+18
2023-01-03Respect --[no-]misaligned command-line flagAndrew Waterman1-8/+6
2023-01-03Merge pull request #1200 from riscv-software-src/mmio_pteAndrew Waterman1-18/+5
Support accessing PTEs through mmio_load/mmio_store
2023-01-03Pull pte load/store into methods of mmu_tJerry Zhao1-18/+5
2023-01-03Add method to probe which memory regions are reservableJerry Zhao1-4/+9
Default reservable regions is the same as before
2023-01-03Specify addresses are physical for simif_t member functionsJerry Zhao1-11/+11
2022-12-23Add mmio_fetch to simif_t to distinguish between fetch/load for mmio accessesJerry Zhao1-1/+9
2022-12-15Add config.h includes directly to source files instead of relying on header ↵Jerry Zhao1-0/+1
chaining This step is to ensure that removing config.h out of headers will not cause regressions.
2022-12-15Rename memif_endianness_t to endianness_tJerry Zhao1-3/+3
2022-12-01Convert triggers::module_t::detect_memory_access_match to std::optionalScott Johnson1-5/+5
Goal is to remove match_result_t.fire field to eliminate dont-care fields when fire=false.
2022-12-01triggers: refactor: rename memory_access_match() to detect_memory_access_match()YenHaoChen1-1/+1
2022-11-30triggers: refactor: let action be part of match_result_tYenHaoChen1-4/+3
2022-11-30triggers: refactor: let match_result_t be a struct with fire and timing ↵YenHaoChen1-14/+11
variables Mapping of previous and revised match_result_t data type: ------------------------------------------- Previous Revised MATCH_NONE fire=false (don't care timing) MATCH_MATCH_FIRE_BEFORE fire=true,timing=TIMING_BEFORE MATCH_MATCH_FIRE_AFTER fire=true,timing=TIMING_AFTER
2022-10-25Remove set_target_endianness | add --big-endian flagJerry Zhao1-2/+5
Set target endianess in constructors
2022-10-19Remove require_alignment flag from loadsAndrew Waterman1-2/+2
The last remaining use was LR, which we can identify through other means.
2022-10-19Fix imprecise exception on LR to MMIO spaceAndrew Waterman1-1/+5
The old implementation performed the load before checking whether the memory region was valid for LR. So, for LR to MMIO, we would action side effects before raising the exception, which is not precise.
2022-10-19do memcpy only for actually_store in store_slow_path_intrapageWeiwei Li1-2/+4
2022-10-14In triggers, use optional<data> instead of {has_data, data}Andrew Waterman1-7/+7
2022-10-13Remove unused field matched_t::dataAndrew Waterman1-2/+2
2022-10-06Don't use reexecution as the means to implement trigger-afterAndrew Waterman1-1/+4
The scheme was based on the notion that memory accesses are idempotent up until the point the trigger would've been hit, which isn't true in the case of side-effecting loads and data-value triggers. Instead, check the trigger on the next instruction fetch. To keep the perf overhead minimal, perform this check on the I$ refill path, and ensure that path is taken by flushing the I$.
2022-10-06Fix endianness bug in fetch triggersAndrew Waterman1-2/+1
Instruction fetch is always little-endian.
2022-10-06DRY in checking triggersAndrew Waterman1-26/+27
2022-10-06Move uncommon-case fetch functionality into fetch_slow_pathAndrew Waterman1-8/+24
2022-10-06Move all uncommon-case store functionality into store_slow_pathAndrew Waterman1-8/+35
As a side effect, misaligned stores now behave the same as aligned stores with respect to triggers: only the first byte is checked.
2022-10-06Move all uncommon-case load functionality into load_slow_pathAndrew Waterman1-5/+32
As a side effect, misaligned loads now behave the same as aligned loads with respect to triggers: only the first byte is checked.
2022-10-05Remove unused variable to fix buildAndrew Waterman1-1/+0
2022-10-05Merge pull request #1105 from YenHaoChen/pr-trigger-priorityAndrew Waterman1-8/+17
Fix trigger priority
2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-09-30Check trigger only with actually_storeYenHaoChen1-5/+7
The data value of the function store_slow_path() is meaningful only when the actually_store=true. Otherwise, the data value is a hollow value of 0, which may result in unintended trigger matching.
2022-09-30Fix priority of mcontrol trigger store address/data beforeYenHaoChen1-2/+2
The spec defines that the mcontrol store address/data has a higher priority over page fault and address misalignment (Debug spec, Table 5.2). Thus, the trigger checking should be before the translation and alignment checking. The previous implementation checks the trigger after the translation and alignment, resulting in incorrect priority. For instance, when page fault and trigger occur on the same instruction, the previous implementation will choose to raise the page fault, which contradicts the priority requirement. This commit moves the trigger checking before the misaligned checking and translation. The trigger will fire on the instruction instead of the page fault in the above case.
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