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This passes our developer test suite, when comparing output
(signature) against the SAIL implementation.
If any corner-cases require additional changes after ACT goes
upstream, we can apply an add-on patch.
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We don't model any sources of RNMI, so this is mostly vestigial.
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Maintain a shadow structure of isa_parser_t::extension_table,
processor_t::extension_enable_table, which tracks whether such
extensions have been dynamically enabled or disabled.
Sanity-check that `extension_enabled_const` honors its contract.
The use of `mutable` is somewhat unfortunate, but we think it's
acceptable here because the only thing that's mutating is this
sanity-checking code, not visible to any consumer of this class.
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This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
for the proposed specification and usage details.
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Make the ISA parser understand the Svadu extension.
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Now that we guarantee that max_isa and extension_table are synchronized,
we only need to check the latter.
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We know its size at compile time.
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Add new accessors that accept the isa_extension_t enum.
Retain the original ones that accept unsigned char to avoid churn.
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The isa_extension_t enum already has 44 extensions. In not too long,
the enum will grow in size to 65, when it will collide with the 'A'
extension. Fix that preemptively by starting after 'Z'.
This approach will run out of steam at 165 extensions because we are
using `unsigned char` to represent extensions, but opefully we will have
retired by that point.
In seriousness, we will probably need to refactor the extension_enabled
logic at some point in the future (e.g. when the configuration structure
is finally added) and at that point we should lift the `char` limit.
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add support for sscofpmf extension v0.5.2
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Add space between ')' and '{'
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since spike doesn't truly support counting of hardware performance events,
only csr related read/write functions is supported currently
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The change makes [v]satp.asid and hgatp.vmid writtable and supports
maximum length for rv32 and rv64. Software could write and read the
satp.asid to get the valid length or check if the core supports
asid/vmid or not. However, there is no official way to describe this hardware
capability (device tree or something else). Two implementation flags
are also added for future use and enabled by default.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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The main motivation for this is that we want to move the ISA parsing
logic to run before we even construct a simulator. That's probably a
bit nicer if we don't depend on the processor header.
It also means that we can stop depending on processor.h in disasm.cc
or spike_log_parser.cc (both through disasm.h), which feels a bit
cleaner: making sense of an instruction trace shouldn't really require
knowledge of the internal state of a processor.
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