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2023-11-16Fix FMVP.D.X implementationAndrew Waterman1-1/+1
Resolves #1507
2023-11-02add halfword width amo instructionsVed Shanbhogue20-20/+31
2023-10-30add byte width amo instructionsVed Shanbhogue10-0/+31
2023-10-18Spike support for the Zalasr extensionbrs8-0/+18
2023-10-18add zcmop extension instructionsVed Shanbhogue2-2/+7
2023-10-16vamo: remove instruction implementationChih-Min Chao36-72/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2023-09-01fix condition of executing cbo.inval as a flush operationviktoryou1-3/+3
Signed-off-by: viktoryou <143797577+viktoryou@users.noreply.github.com>
2023-06-19Zvk: Implement Zvksh, vector SM3 Hash FunctionEric Gouriou2-0/+99
Implement the Zvksh sub-extension, "ShangMi Suite: SM3 Hash Function Instructions": - vsm3me.vv, message expansion, - vsm3c.vi, compression rounds. This also introduces a SM3 specific header for common logic. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Albert Jakieła <aja@semihalf.com> Co-authored-by: Kornel Dulęba <mindal@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvksed, vector SM4 Block CipherEric Gouriou4-1/+140
Implement the Zvksed sub-extension, "ShangMi Suite: SM4 Block Cipher": - vsm4k.vi, vector SM4 key expansion, - vsm4r.{vs,vv}, vector SM4 rounds. This also introduces a header for common vector SM4 logic. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Albert Jakieła <aja@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvkned, vector AES single roundEric Gouriou11-0/+502
Implement the Zvkned extension, "NIST Suite: Vector AES Encryption & Decryption (Single Round)". - vaeskf1.vi: AES forward key scheduling, AES-128. - vaeskf2.vi: AES forward key scheduling, AES-256. - vaesz.vs: AES encryption/decryption, 0-th round. - vaesdm.{vs,vv}: AES decryption, middle rounds. - vaesdf.{vs,vv}: AES decryption, final round. - vaesem.{vs,vv}: AES encryption, middle rounds. - vaesef.{vs,vv}: AES encryption, final round. An extension specific header containing common logic is added. Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvknh[ab], NIST Suite: Vector SHA-2Eric Gouriou3-0/+186
Implement the instructions part of the Zvknha and Zvknhb sub-extensions: - vsha2ms.vv, message schedule - vsha2ch.vv / vsha2cl.vv, compression rounds A header files for common macros is added. Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvkg, Vector GCM/GMAC instructionEric Gouriou2-0/+70
Implement the proposed instruction in Zvkg, vghmac.vv, Vector Carryless Multiply Accumulate over GHASH Galois-Field. The instruction performs one step of GHASH routine as described in "NIST Special Publication 800-38D" a.k.a the AES-GCM specification. The logic was written to closely track the pseudo-code in the Zvk specification. Signed-off-by: Eric Gouriou <ego@rivosinc.com> Co-authored-by: Kornel Duleba <mindal@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvbc extension, vectory carryless multiplactionEric Gouriou4-0/+80
Implement the Zvbc instructions - vclmul.{vv,vx}, vector carryless multiply low - vclmulh.{vv,vx}, vector carryless multiply high Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Zvk: Implement Zvbb, Vector Bit-manipulation for CryptographyEric Gouriou16-0/+239
Implement the proposed instructions in Zvbb: - vandn.{vv,vx}, vector bitwise and-not - vbrev.v, vector bit reverse in element - vbrev8.v, vector bit reverse in bytes - vrev8.v, vector byte reverse - vctz.v, vector count trailing zeros - vclz.v, vector count leading zeros - vcpop.v, vector population count - vrol.{vv,vx}, vector rotate left - vror.{vi,vv,vx}, vector rotate right - vwsll.{vi,vv,vx} vector widening shift left logical A new instruction field, 'zimm6', is introduced, encoded in bits [15, 19] and [26].. It is used by "vror.vi" to encode a shift immediate in [0, 63]. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-06-19Implement Zacas extension.Gianluca Guida3-0/+73
2023-06-18Remove Xbitmanip from instructions that belong to multiple extensionsAndrew Waterman14-30/+16
2023-06-18Remove instructions that belong only to XbitmanipAndrew Waterman45-347/+0
2023-06-06Merge pull request #1321 from plctlab/plct-bf16-devAndrew Waterman10-4/+34
Add support for BF16 extensions
2023-06-01dscr.ebreakh is now dcsr.ebreakv[su]Tim Newsome2-8/+12
This change was made ages ago in the spec. I did not actually test that the new privilege checks in ebreak and c.ebreak are correct, but all the existing debug tests still pass.
2023-05-29Add flh/fsh/fmv_h_x/fmv_x_h instructions to Zvfbfmin/Zvfbfwma extensionsWeiwei Li4-4/+4
2023-05-29Add support for new instructions of Zvfbfwma extensionWeiwei Li2-0/+10
2023-05-29Add support for new instructions of Zvfbfmin extensionWeiwei Li2-0/+10
2023-05-29Add support for new instructions of Zfbfmin extensionWeiwei Li2-0/+10
2023-05-25Refactor set_privilege to subsume set_virtAndrew Waterman4-8/+4
This cleans up the code and avoids bugs like #1365.
2023-05-25Redo sret to put set_virt/set_privilege togetherScott Johnson1-3/+4
2023-05-25Implement dcsr.v and make DRET use itAndrew Waterman1-0/+1
Resolves #1365
2023-05-09Merge pull request #1357 from ptomsich/ptomsich/1312-fix-fcvtmod_w_d-exceptionsAndrew Waterman1-1/+3
Zfa: fix exception behaviour for fcvtmod.w.d
2023-05-09Merge pull request #1356 from ptomsich/ptomsich/1355-fix-fleq-fltq-exceptionsAndrew Waterman8-0/+8
Zfa: fix missing set_fp_exceptions for fleq/fltq
2023-05-09Zfa: fix missing set_fp_exceptions for fleq/fltqPhilipp Tomsich8-0/+8
2023-05-09Zfa: fix exception behaviour for fcvtmod.w.dPhilipp Tomsich1-1/+3
2023-05-09Zfa: fix bitpatterns for fli.q (entries 7, 18-25)Philipp Tomsich1-9/+9
Ref #1327 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-05-09Zfa: fli.q requires 'Q' not 'D'Philipp Tomsich1-1/+1
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-05-09Merge pull request #1353 from ptomsich/ptomsich/1351-Zfa-fix-NX-fround-familyAndrew Waterman8-8/+8
Zfa: fix NX handling for the fround/froundnx family
2023-05-09Zfa: fix NX handling for the fround/froundnx familyPhilipp Tomsich8-8/+8
The initial implementation (together with the SAIL code and the tests) had gotten the NX variants backwards (as in 'an inexact result is ok' vs. 'set NX is inexact'). Update all 4 instructions. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-04-15Fix comments error in vfncvt_*_w.hWeiwei Li4-4/+4
2023-04-15Remove unused parameter for macro in v_ext_macro.hWeiwei Li9-18/+0
2023-04-03Implement Zfa.Philipp Tomsich33-0/+420
This passes our developer test suite, when comparing output (signature) against the SAIL implementation. If any corner-cases require additional changes after ACT goes upstream, we can apply an add-on patch.
2023-03-20Implement Smrnmi extensionAndrew Waterman1-0/+15
We don't model any sources of RNMI, so this is mostly vestigial.
2023-02-21Remove redundant RVE related check in cm.mva01s and cm.mvsa01Weiwei Li2-6/+0
r1s/r2s > 16 when r1sc/r1sc >2. This will also trigger illegal instruction exception by CHECK_REG if RVE is enabled
2023-02-21Add r1s != r2s check for cm.mvsa01Weiwei Li1-0/+1
2023-02-21Update fields name for sreg1/sreg2Weiwei Li2-6/+6
2023-01-31Zicond: implement Zicond (conditional integer operations)Philipp Tomsich2-0/+4
This implements the Zicond (conditional integer operations) extension, as of version 1.0-draft-20230120. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf for the proposed specification and usage details.
2022-12-05Merge pull request #1162 from riscv-software-src/sfenceAndrew Waterman2-3/+2
SFENCE.W.INVAL and SFENCE.INVAL.IR should check privilege mode
2022-12-05SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modesAndrew Waterman1-0/+1
See discussion on https://lists.riscv.org/g/tech-privileged/message/1213
2022-12-05Simplify implementation of SFENCE.W.INVALAndrew Waterman1-3/+1
For Spike, this instruction merely performs exception checks, just like SFENCE.INVAL.IR. So, implement it in terms of SFENCE.INVAL.IR.
2022-11-28Merge pull request #1156 from plctlab/plct-zce-fixAndrew Waterman1-1/+1
Fix support for Zc*
2022-11-28Fix field extract for jvt.baseWeiwei Li1-1/+1
2022-11-21When resuming from debug mode, clear mstatus.MPRV if the new privilege mode ↵YenHaoChen1-0/+2
is less than M-mode (#1149)
2022-11-17add support for zcmtWeiwei Li1-0/+23
add suport for jvt: Table entries follow the current data endianness
2022-11-17add support for zcmpWeiwei Li6-0/+50
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