riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2019-11-11	rvv: add reg checking rule for ldst	Chih-Min Chao	1	-1/+2
	include 1. unit-stride 2. strided 3. indexed 4. fault-first Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11	rvv: remove configuable tail-zero	Chih-Min Chao	1	-7/+4
	tail zero feature has been removed after v0.8-draft Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-07-19	Check vtype.vill for all vector instructions except vsetvl[i]	Andrew Waterman	1	-0/+1

2019-06-18	rvv: add load/store instructions	Chih-Min Chao	1	-0/+27
	based on v-spec 0.7.1, support section: 7 element size: 8/16/32/64 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Zakk Chen <zakk.chen@sifive.com>