| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-08-10 | Add space between if/while/switch and '(' | Weiwei Li | 1 | -6/+6 |
| 2020-04-24 | rvv: add vfslide1[down|up].vf and refine checking rule | Chih-Min Chao | 1 | -9/+5 |
| 2020-04-09 | rvv: vslide[1]up now allows mask overlap when LMUL=1 | Chih-Min Chao | 1 | -1/+1 |
| 2019-12-20 | rvv: change vmerge/vslideup register checking rule | Chih-Min Chao | 1 | -1/+1 |
| 2019-11-11 | rvv: add reg checking rule to vslide instructions | Chih-Min Chao | 1 | -2/+4 |
| 2019-06-18 | rvv: add integer/fixed-point/mask/reduction/permutation instructions | Chih-Min Chao | 1 | -0/+32 |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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