| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-07-29 | rvv: add new whole reg load/store instructions | Chih-Min Chao | 1 | -0/+2 |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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