| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-10-25 | Change remaining vector FP16 instructions to require Zvfh | Andrew Waterman | 1 | -1/+1 |
| 2021-12-09 | Simplify vfncvt | eopXD | 1 | -23/+9 |
| 2021-09-27 | Convert frm & fflags to csr_t | Scott Johnson | 1 | -3/+3 |
| 2021-09-08 | Rename supports_extension() to extension_enabled() | Scott Johnson | 1 | -3/+3 |
| 2020-09-22 | rvv: fix vfncvt/vfwcvt type checking | Chih-Min Chao | 1 | -1/+11 |
| 2020-08-31 | rvv: trigger exp for illegal ncvt/wcvt eew | Chih-Min Chao | 1 | -1/+1 |
| 2020-05-28 | rvv: add e8 type for narrow/widen conversion | Chih-Min Chao | 1 | -0/+4 |
| 2020-05-04 | rvv: fp16: support conversion instrucitons | Chih-Min Chao | 1 | -8/+8 |
| 2020-01-22 | commitlog: rvv: add commitlog support to float instrunctions | Chih-Min Chao | 1 | -1/+1 |
| 2020-01-13 | rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32 | Chih-Min Chao | 1 | -1/+5 |
| 2019-12-20 | rvv: rename vfncvt suffix and add rod rouding type | Chih-Min Chao | 1 | -0/+6 |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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