| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2021-10-14 | Split 'P' to EXT_ZPN and friends (#830) | marcfedorow | 1 | -1/+1 | |
| * Added ZMMUL extension * Splitted P-ext to its zeds * Typo fix | |||||
| 2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -0/+1 | |
| Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha | |||||
| 2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -1/+1 | |
| Sorry, everyone. | |||||
| 2014-09-27 | Avoid use of __int128_t | Andrew Waterman | 1 | -6/+2 | |
| It is nonstandard, and GCC doesn't support it on 32-bit platforms. The resulting code for MULH[[S]U] is crappier, but that doesn't really matter, as these instructions are dynamically infrequent. | |||||
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -2/+2 | |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+8 | |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -8/+0 | |
| 2011-04-16 | [sim] removed undefined behavior for non-canonical inputs | Andrew Waterman | 1 | -1/+1 | |
| 2011-04-08 | [sim] fixed multiply-high in rv32 | Andrew Waterman | 1 | -1/+1 | |
| 2011-01-25 | [sim,opcodes] add mulhsu instruction | Andrew Waterman | 1 | -0/+8 | |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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