| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-11-17 | add support for zca zcd and zcf | Weiwei Li | 1 | -1/+1 | |
| 2018-04-04 | Revert "Fix for issue #183: No illegal instruction exception for c.sxxi ↵ | Andrew Waterman | 1 | -1/+1 | |
| instructions encoded with zero shift amount" This reverts commit be0555d585b332fd0496affe559c0a5a4e7e5644. See #190 | |||||
| 2018-03-16 | Fix for issue #183: No illegal instruction exception for c.sxxi instructions ↵ | Shubhodeep Roy Choudhury | 1 | -1/+1 | |
| encoded with zero shift amount | |||||
| 2015-10-02 | work towards rvc 1.8 | Andrew Waterman | 1 | -0/+3 | |
| 2015-09-04 | Move towards RVC v1.8 | Andrew Waterman | 1 | -3/+0 | |
| 2015-05-31 | New RV64C proposal | Andrew Waterman | 1 | -0/+3 | |
| 2013-07-26 | Rip out RVC for now | Andrew Waterman | 1 | -5/+0 | |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+5 | |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -5/+0 | |
| 2011-04-24 | [xcc,sim,opcodes] added more RVC instructions | Andrew Waterman | 1 | -0/+5 | |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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