riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2022-10-04	Suppress most unused variable warnings	Andrew Waterman	1	-1/+1

2015-09-08	Refer to LICENSE in some newer source files	Andrew Waterman	1	-0/+2

2014-11-25	Factor out the dummy RoCC accelerator	Andrew Waterman	1	-4/+3

2013-10-18	refactor disassembler, and add hwacha disassembler	Yunsup Lee	1	-0/+3

2013-10-16	use reset virtual method	Yunsup Lee	1	-1/+1

2013-10-15	Propogate the reset call to the extensions as well. Add reset function to ↵	Stephen Twigg	1	-0/+1
	extensions (demonstration in dummy acc)
2013-08-13	Implement RoCC and add a dummy RoCC	Andrew Waterman	1	-0/+33
	Enable it with --extension=dummy