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2022-05-05Factor out P extension macros into their own headerfactor-out-macrosAndrew Waterman1-500/+1
No functional change.
2022-05-05Factor out V extension macros into their own headerAndrew Waterman1-2069/+1
No functional change.
2022-04-14fix style problems in decode.h and processor.ccWeiwei Li1-266/+266
2022-04-09Replaced vector loop compare body with newly defined macro4vtomat1-90/+11
This commit uses new macro to replace loop compare body to enhance code reuse.
2022-04-09Adding new macro to replace repetitive code4vtomat1-0/+15
2022-02-23rvv: add missing elen checking for some ldst (#927)Chih-Min Chao1-0/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2022-01-30add instructions function for cmoliweiwei1-0/+14
prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
2022-01-25Add more assertion for fcvt (#910)Yueh-Ting (eop) Chen1-0/+2
2022-01-10Merge pull request #899 from riscv-software-src/rv32eAndrew Waterman1-2/+4
Add RV32E/RV64E base ISA support
2022-01-09Changes to be cleaner wrt. -WextraAndrew Waterman1-1/+1
h/t @jerinjoy See #901
2022-01-06Support RV32E/RV64E base ISAsAndrew Waterman1-2/+4
2021-12-27Fix check for fcvt (#897)Yueh-Ting (eop) Chen1-9/+18
2021-12-23Fix check for fcvt (#894)Yueh-Ting (eop) Chen1-2/+2
2021-12-21Add missing check for floating-point merge instructions (#893)Yueh-Ting (eop) Chen1-4/+6
2021-12-17Merge pull request #881 from eopXD/simplify-float-convertAndrew Waterman1-30/+145
Simplify float convert instructions
2021-12-12Fix minor type-o (#885)Yueh-Ting (eop) Chen1-2/+2
2021-12-09Simplify vfwcvteopXD1-39/+50
2021-12-09Simplfy vfcvteopXD1-0/+34
2021-12-09Simplify vfncvteopXD1-0/+70
2021-12-07Merge pull request #879 from eopXD/simply-instsAndrew Waterman1-42/+124
Simply floating point parameters and merge operations
2021-12-07Simplify vadc and vsbc (#876)Yueh-Ting (eop) Chen1-6/+10
2021-12-07Merge pull request #868 from eopXD/simplify-narrowing-instAndrew Waterman1-47/+54
Simplify narrowing instruction
2021-12-08Simplify vmerge, vfmergeeopXD1-5/+66
2021-12-08Simplify floating point compare instructionseopXD1-13/+35
2021-12-08Simply parameters for floating-point instructionseopXD1-24/+23
2021-12-06Simplify vmadc and vmsbc (#877)Yueh-Ting (eop) Chen1-8/+19
2021-11-30Simplify mulhsu (#870)Yueh-Ting (eop) Chen1-0/+47
2021-11-28Have nclip_{wv/wx/wi} use different macroseopXD1-41/+48
This allows them to share PARAM macro with narrowing right-shift instructions. Rename VV_NSHIFT_PARAMS -> VV_NARROW_PARAMS so nclip, nsra, nsrl can share it. (Same goes to VX_NSHIFT_PARAMS and VI_NSHIFT_PARAMS)
2021-11-28Eliminate redundant parameters for narrowing integer right shift instructionseopXD1-6/+6
2021-11-27Simplify single-width averaging add and subtract (#867)Yueh-Ting (Eop) Chen1-76/+28
2021-11-08Move definitions of P and require macrosAndrew Waterman1-2/+0
Avoids namespace conflicts with Boost. Fixes #820 in a better way.
2021-10-25Fixed a segmentation fault bug (#842)eric-xtang10081-1/+1
After excuting vector load/store whole register instructions, spike would be crashed when excuted the next vector instruction. Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>
2021-10-14Split 'P' to EXT_ZPN and friends (#830)marcfedorow1-12/+12
* Added ZMMUL extension * Splitted P-ext to its zeds * Typo fix
2021-10-06Don't write vxsat unless it's actually being set to 1Scott Johnson1-1/+1
As requested by @marcfedorow: https://github.com/riscv-software-src/riscv-isa-sim/issues/823#issuecomment-936509476 If mstatus.VS exists (i.e. Vector extension is enabled), it will no longer be set to Dirty unless the instruction actually sets vxsat. The mstatus.VS change only affects instructions in the P extension, since Vector instructions will write other vector state and therefore still set mstatus.VS=Dirty. This also affects the commit log. Instructions that don't saturate will no longer show a write to vxsat.
2021-09-29Remove no-longer-needed csr_read_only check in validate_csr()Scott Johnson1-5/+1
All CSR permissions checks now occur inside the csr_t::verify_permissions() methods. This reverts commit 62526773c0a30a41356fbfce1db0fb8a32771c30.
2021-09-29Convert vl to csr_tScott Johnson1-17/+17
Adds commit log events for vl to many vector instructions.
2021-09-29Convert vstart to csr_tScott Johnson1-53/+53
Adds commit log events for vstart to many vector instructions.
2021-09-29Convert vxsat to csr_tScott Johnson1-1/+1
Adds commit log events for vxsat to many vector instructions.
2021-09-27Remove unnecessary double-setting of mstatus.FS=DirtyScott Johnson1-1/+0
fflags->write() already sets that.
2021-09-27Convert frm & fflags to csr_tScott Johnson1-6/+6
Adds proper logging of fflags on FP arithmetic ops.
2021-09-08Move enable detections into sstatus_csr_tScott Johnson1-3/+3
To DRY up code in decode.h.
2021-09-08Move dirtying logic into sstatus_csr_tScott Johnson1-3/+3
2021-09-08Rename supports_extension() to extension_enabled()Scott Johnson1-10/+10
Because this checks the dynamic run-time state of misa, let's use the same language as the misa spec (enabled vs disabled). Calling it supports_extension() could be confused for a check of the static configuration of Spike (i.e. the --isa string), which it was not.
2021-09-08Convert mstatus into csr_t familyScott Johnson1-3/+3
Step 3 of plan described in csrs.h.
2021-09-08Remove no-longer-necessary explicit setting of *status.SD bitScott Johnson1-3/+3
Since the previous commit, the SD bit will get set properly by proc->set_csr(CSR_MSTATUS,...) in sstatus_proxy_csr_t::unlogged_write() for sstatus, and by vsstatus_csr_t::backdoor_write() for vsstatus.
2021-09-08Convert vsstatus to csr_t familyScott Johnson1-3/+3
Makes a mess out of the tracing though, because of how every toggle of the VBit swaps mstatus and vsstatus.
2021-09-08Extract function for dirty_mstatus()Scott Johnson1-7/+3
This will eventually become a method in a new csr_t subclass.
2021-07-26Fix several bugs in P-extension register-pair handlingAndrew Waterman1-9/+7
- Words shouldn't be swapped based on enddianness; the lower-numbered register always holds the low-order bits. - Check for alignment, which also fixes a buffer overflow. - Handle x0 correctly: read as zero, discard writes.
2021-07-26decode: op: remove quad related macro and defineChih-Min Chao1-79/+0
Let git keep the legacy code Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-06-02Fix ambiguous if/else warningAndrew Waterman1-1/+1
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