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2021-06-02Fix CSR read-only check regression introduced in 463001198Andrew Waterman1-1/+5
2021-05-10Support RISC-V p-ext-proposal v0.9.2 (#637)ChunPing Chung1-0/+509
* rvp: add 8/16 bits add/sub simd instructions * rvp: add 8/16 bits shift simd instructions * rvp: add 8/16 bits compare simd instructions * rvp: add 8/16 bits multiply simd instructions * rvp: add 8/16 bits misc simd instructions * rvp: add 8 bits unpacking simd instructions * rvp: update suppported extention and add restriction * rvp: update encoding.h and riscv.mk.in * rvp: disasm: add simd instruction support * rvp: update readme for p-ext simd instructions * rvp: fix rvp support version * rvp: update encoding.h generated from riscv-opcode p-ext branch * rvp: rename some macro argument * rvp: add pk[bb,bt,tt,tb][16,32] instructions * rvp: add kadd32, [su]maqa[_su] instructions * rvp: fix missing initial value of pd * rvp: add msw 32x32 multiply & add instructions * rvp: change to use extract64 * rvp: add msw 32x16 multiply & add instructions * rvp: fix some style * rvp: change reduction marcro definition * rvp: add signed 16x32 add/subtract instructions * rvp: use stdint to replace hardcode max/minimum * rvp: refactor some p-ext macro code * rvp: add partial simd miscellaneous instructions * rvp: add signed 16 x 64 add/subtract Instructions * rvp: add 64-bit add & sub instructions * rvp: add 32-bit mul with 64-bit add/sub instructions * rvp: add 16-bit mul with 64-bit add/sub instructions * rvp: disasm: add 64 bit profile instruction support * rvp: add Q15 saturation instructions * rvp: fix kmar64/kmsr64 saturation behavior * rvp: add 32-bit computation instructions * rvp: add rdov/clrov and fix khm16 behavior of setting OV flag * rvp: add non simd miscellaneous instructions * rvp: add Q31 saturation instructions * rvp: disasm: add non-simd instruction support * rvp: add 32 bits add/sub simd instructions * rvp: fix left shift saturation bug * rvp: add 32 bits shift simd instructions * rvp: add rv64 only Q15 simd instructions * rvp: add rv64 only 32-bit multiply instructions * rvp: add rv64 only 32-bit miscellaneous instructions * rvp: add rv64 only 32-bit mul & add instructions * rvp: add rv64 only 32-bit parallel mul & add instructions * rvp: add rv64 only non-simd 32-bit shift instructions * rvp: disasm: remove redundant tab * rvp: disasm: add rv64 only instructions support * rvp: change ov csr to ucode to match v0.5.2 spec * rvp: update readme for p-ext 0.5.2 * rvp: update to p-ext v0.9.1 * rvp: update to p-ext v0.9.2 * rvp: update readme for p-ext 0.9.2 * rvp: fix macro for PKxx16 & PKxx32 commands. * rvp: fix missing for in PKxxdd macro * Sign-extension for p-ext insns * * Fixed uclipNN insns while sh >> 64 is an UB. * Added missing OV * Added missing sext_xlen * Remove unused macroses * Sign extension for RD_PAIR macro * rvp: remove lost tab Co-authored-by: Mark Fedorov <mark.fedorov@cloudbear.ru>
2021-05-01Improve coding style of logging printfsAndrew Waterman1-1/+2
2021-03-05Fix vsstatus.FS misbehavior (#661)Scott Johnson1-7/+10
* Simplify Boolean logic No functional change intended. * Apply same logic to virtualize sstatus.XS as used for VS and FS Though this macro does not seem to be used anywhere today. * Extract common macro to DRY up code * Dirty both mstatus and vsstatus FP fields Fixes https://github.com/riscv/riscv-isa-sim/issues/660
2021-02-24rvv: add vsetivliChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-24rvv: add vse1/vle1Chih-Min Chao1-12/+12
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-17Fix require_vector_vs() for H-extensionAnup Patel1-1/+1
We should check both MSTATUS.VS and VSSTATUS.VS when updating vector state with virt-on. This patch fixes require_vector_vs() macro accordingly. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2021-02-16fix require fp since spec said <When V=1, both vsstatus.FS and the HS… (#646)francis40961-1/+1
* fix require fp since spec said <When V=1, both vsstatus.FS and the HS-level sstatus.FS are in effect> * fix require fp for logic AND
2021-01-22scalar-crypto: Initial spike support for v0.8.1 (#635)Ben Marshall1-0/+3
Brief: - This commit adds spike support for the scalar cryptography extension. See the riscv-crypto repository (https://github.com/riscv/riscv-crypto) for more information on this extension. - It is based on the experimental patch which has so far been kept in the riscv-crypto repository. Now that scalar crypto is nearly at the "freeze" stage and entering opcode consistency review, it makes sense to start upstreaming our experimental version. - In terms of compiler support - we are using an experimental patch in the riscv-crypto repository at the moment, others are working on an upstream appropriate version. Details: - Add support for dedicated scalar crypto instructions. - Add very basic support for the entropy source (entropy_source.h). Much of the behaviour of this is implementation specific. This model aims to provide the bare minimum of functionality which can be used to quickly develop software. It uses /dev/urandom as its entropy source for now. - Scalar crypto is unique in that it _borrows_ instructions from the Bitmanipulation extension. This is currently _not_ encoded in the patch, as I didn't want to damage anything in Bitmanip which is currently under review. However, I've added a macro in riscv/decode.h called "require_either_extension(A,B)", which allows instructions to be valid opcodes iff they are in one or both extensions. On branch scalar-crypto Changes to be committed: modified: README.md modified: riscv/decode.h modified: riscv/encoding.h new file: riscv/entropy_source.h new file: riscv/insns/aes64im.h new file: riscv/insns/aes64ks1i.h new file: riscv/insns/aes64ks2.h new file: riscv/insns/aes_common.h new file: riscv/insns/aesds.h new file: riscv/insns/aesdsm.h new file: riscv/insns/aeses.h new file: riscv/insns/aesesm.h new file: riscv/insns/sha256sig0.h new file: riscv/insns/sha256sig1.h new file: riscv/insns/sha256sum0.h new file: riscv/insns/sha256sum1.h new file: riscv/insns/sha512sig0.h new file: riscv/insns/sha512sig0h.h new file: riscv/insns/sha512sig0l.h new file: riscv/insns/sha512sig1.h new file: riscv/insns/sha512sig1h.h new file: riscv/insns/sha512sig1l.h new file: riscv/insns/sha512sum0.h new file: riscv/insns/sha512sum0r.h new file: riscv/insns/sha512sum1.h new file: riscv/insns/sha512sum1r.h new file: riscv/insns/sm3p0.h new file: riscv/insns/sm3p1.h new file: riscv/insns/sm4_common.h new file: riscv/insns/sm4ed.h new file: riscv/insns/sm4ks.h modified: riscv/processor.cc modified: riscv/processor.h modified: riscv/riscv.mk.in
2020-12-14rvv: fix the v[z|s]ext about elmul checking.Dave.Wen1-1/+1
2020-12-14disasm: show fench's predecessor and successorChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-12-04rvv: check the vz/sext's eewDave.Wen1-0/+1
2020-11-11mmu: add impl table and set functionChih-Min Chao1-0/+1
some features are optional to u-arch or could be selectively supported. Add an impl_table to keep implemented feature Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-26rvv: check extra dst for index segment loadChih-Min Chao1-12/+15
each segment register group has to follow overlapping rule Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-06rvv: vamo needs to keep exception index in vstartChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-01decode: only return meaningful bits for insn_t (#561)Chih-Min Chao1-1/+1
The original insn_t has the upper part with extended signed bit when the instruction is fetched from mmu_t::refill_icache. It makes the tval of illegal instruction exception wrong. ref: As the spec 3.1.17 says, after an illegal instruction trap, mtval will contain the shortest of: 1. the actual faulting instruction 2. the first ILEN bits of the faulting instruction 3. the first XLEN bits of the faulting instruction The value loaded into mtval is right-justified and all unused upper bits are cleared to zero. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-22rvv: fix vfncvt/vfwcvt type checkingChih-Min Chao1-1/+6
for each case, use explicit type checking Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-20Don't throw virtual instruction exceptions for unimplemented CSRsAndrew Waterman1-13/+1
2020-09-15Populate tval registers on illegal-/virtual-instruction trapsAndrew Waterman1-6/+6
2020-08-31rvv: relax checking for vs1Chih-Min Chao1-0/+29
vs1 is sub-op Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: trigger exp for illegal ncvt/wcvt eewChih-Min Chao1-1/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-31rvv: check invalid frm for floating operationsChih-Min Chao1-0/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao1-16/+20
except for load/store instructions 0 : all instruction can't have non-zero vstart not 0 : all instruction can have non-zero vstart if it is not required vstart must be zero in spec the default value is 1 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29f16: fix Nan-Box macroChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: fix frac_lmul get functionChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao1-5/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: remove veew/vemul stateChih-Min Chao1-27/+25
They aren't arch state Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao1-0/+60
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-28Incorporate RVV 1.0 vtype layout changeAndrew Waterman1-2/+2
2020-07-09Implement hypervisor CSRs read/writeAnup Patel1-3/+12
We add newly defined hypervisor CSRs and allow M/HS-mode to access these CSRs. The MRET, SRET, ECALL and WFI instructions have also been updated so that virt-to-novirt switch and exception cause is based on HART virtualization state. Subsequent patches will implement two-stage page tables, HFENCE instructions and HSV/HLV instructions. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao1-3/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-25rvv: remove unecessary accessChih-Min Chao1-3/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-15remove the redundant code (#488)Dave Wen1-1/+0
2020-06-11rvv: fix index and amo overlapping ruleChih-Min Chao1-4/+23
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-11rvv: add widen overlapping helper and related widen ruleChih-Min Chao1-8/+52
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-11rvv: fix comparison and narrow overlapping ruleChih-Min Chao1-3/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-04rvv: fix compilation warningChih-Min Chao1-6/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: use zvqmac to enable vector qmacChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: apply new overlapping and align macroChih-Min Chao1-53/+46
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: add e8 type for narrow/widen conversionChih-Min Chao1-5/+24
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: add new explicit eew load/store instructionsChih-Min Chao1-108/+122
1. unit 2. stride 3. index 4. fault-first Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: add amo instructionsChih-Min Chao1-0/+43
use --isa=rv64gcv_zvamo to enable it Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: add new singed/unsiged extension instructionsChih-Min Chao1-0/+40
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: wrap align and overlap checking macroChih-Min Chao1-4/+31
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: remove vmlenChih-Min Chao1-11/+10
vmlen has be changed to 1 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: handle inactive and NaN case for vfredsumChih-Min Chao1-2/+51
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-04rvv: fp16: support vfwxxx.[wv][vf] instructionsChih-Min Chao1-19/+42
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-04rvv: fp16: support conversion instrucitonsChih-Min Chao1-0/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-04rvv: fp16: support reduction instructionsChih-Min Chao1-9/+38
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-04rvv: fp16: support comparison instructionsChih-Min Chao1-2/+9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
generated by cgit v1.1 at 2024-10-20 01:16:31 +0000