aboutsummaryrefslogtreecommitdiff
path: root/riscv/csrs.h
AgeCommit message (Collapse)AuthorFilesLines
2024-04-29Merge pull request #1648 from YenHaoChen/pr-hstateenAndrew Waterman1-1/+3
Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0
2024-04-29add hlvx pmp protect to fix issue 1557xinyuwang-sifive1-1/+1
2024-04-23Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0YenHaoChen1-1/+3
The specification states that writes to read-only bits in a RW CSR are ignored. The hstateen*[n] bits are read-only when mstateen*[n]=0. This PR proposes ignoring writes to read-only hstateen*[n] bits when mstateen*[n]=0 instead of writing the bits to 0.
2024-04-18Add Zicfiss extension from CFI extension, v0.4.0SuHsien Ho1-0/+7
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name. 2. Add new software exception with tval 3 for shadow stack. 3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d. 4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding. 5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page. 6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag. 7. Check special pte(xwr=010) of SS page.
2024-04-09Ignore writes to henvcfg fields (PBMTE, STCE, and ADUE) when read-only 0YenHaoChen1-0/+3
The henvcfg fields, i.e., PBMTE, STCE, and ADUE, are read-only 0 when the corresponding bits in menvcfg are 0. Besides the reading behavior, the spec also specified the writing behavior, i.e., ignoring writes. This commit ignores writes to the henvcfg fields when read-only 0. Reference: https://github.com/riscv/riscv-isa-manual/issues/1312
2024-03-06Zicfilp: Preserve expected landing pad state on trapsMing-Yi Lai1-1/+2
2024-03-06Zicfilp: Add CSR fieldsMing-Yi Lai1-0/+6
2024-02-06Fix hvip.VSEIP and hvip.VSTIP, so they don't observe platform-specific ↵YenHaoChen1-1/+12
interrupts or CSR hgeip bits The H extension defines that bits VSEIP, VSTIP, and VSSIP of hvip are writable. (The other bits of hvip are read-only 0.) Only hip.VSSIP (mip.VSSIP) is an alias of hvip.VSSIP. The hip.VSEIP is the logical-OR of hvip.VSEIP, selected bit of hgeip by hstatus.VGEIN, and platform-specific external interrupt signals to VS-level, e.g., from AIA. The hip.VSTIP is the logical-OR of hvip.VSTIP and platform-specific timer interrupt signals to VS-level, e.g., from Sstc. Thus, the read values of hvip.VSEIP and hvip.VSTIP differ from the ones of hip.VSEIP and hip.VSTIP (mip.VSEIP and mip.VSTIP). In other words, the hvip isn't an alias (proxy) of mip. The current aliasing (proxy) implementation does not provide the desired behavior for hvip.VSEIP and hvip.VSTIP. An ISA-level behavior difference is that any platform-specific external and timer interrupt signals directed to VS-level should not be observable through the hvip. For instance, the hvip should not observe the virtual timer interrupt signal from the vstimecmp CSR (Sstc extension), which isn't true in the current implementation. Additionally, the hvip should not observe the virtual external interrupt signal from the IMSIC device (AIA extension). Another ISA-level behavior difference is that the hgeip and hstatus.VGEIN also should not affect hvip.VSEIP, which isn't true in the current implementation. This commit fixes the issue by giving the hvip a specialized class, hvip_csr_t. The hvip_csr_t aliases the hvip.VSSIP to the mip.VSSIP but decouples the hvip.VSEIP and hvip.VSTIP from mip.VSEIP and mip.VSTIP. Additionally, the commit updates the read value of mip to be the logical-OR of hvip.VSEIP, hvip.VSTIP, and other sources.
2023-12-30Add srmcfg CSRVed Shanbhogue1-0/+7
2023-11-24stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in ↵YenHaoChen1-0/+1
HS-mode The spec requires menvcfg.STCE=1 on accessing stimecmp or vstimecmp in a mode other than M-mode. The previous implementation does not check the permission on accessing vstimecmp in HS-mode. This commit fixes the issue by moveing the permission check from virtualized_stimecmp_csr_t to stimecmp_csr_t, which implements the vstimecmp.
2023-08-14rename *envcfg.HADE to *envcfg.ADUEVed Shanbhogue1-1/+1
2023-07-26Add Smcntrpmf functionalityAtul Khare1-1/+21
If Smcntrpmf is enabled, mcycle / minstret increment only if counting for the privilege level isn't inhibited in mcyclecfg / minstretcfg.
2023-07-25Merge pull request #1383 from rivosinc/sscrind_featureAndrew Waterman1-0/+28
Add Smcsrind / Sscsrind support
2023-07-25legalize henvcfg.CBIEYenHaoChen1-1/+1
The value 2 of henvcfg.CBIE is reserved. This commit legalizes it to 0. Reference: https://github.com/riscv/riscv-CMOs/issues/65
2023-07-25legalize senvcfg.CBIEYenHaoChen1-1/+1
The value 2 of senvcfg.CBIE is reserved. This commit legalizes it to 0. Reference: https://github.com/riscv/riscv-CMOs/issues/65
2023-07-25legalize menvcfg.CBIEYenHaoChen1-0/+7
The value 2 of menvcfg.CBIE is reserved. This commit legalizes it to 0 by adding a specialized class envcfg_csr_t. Reference: https://github.com/riscv/riscv-CMOs/issues/65
2023-07-19Add Smcsrind/Sscsrind supportAtul Khare1-0/+28
This adds the following CSRs: miselect (0x350), mireg (0x351), mireg2/3 (0x352, 0x353), mireg4-6 (0x355 - 0x357), siselect (0x150), sireg (0x151), sireg2/3 (0x152, 0x153), sireg4-6 (0x155 - 0x157), vsiselect (0x250), vsireg (0x251), mireg2/3 (0x252, 0x253), vsireg4-6 (0x255 - 0x257). Presently, attempts to read / write from ireg? registers will fail, and future extensions will provide proxy CSR mappings for the respective ?ireg CSRs.
2023-06-01dscr.ebreakh is now dcsr.ebreakv[su]Tim Newsome1-1/+2
This change was made ages ago in the spec. I did not actually test that the new privilege checks in ebreak and c.ebreak are correct, but all the existing debug tests still pass.
2023-05-25Implement dcsr.v and make DRET use itAndrew Waterman1-1/+2
Resolves #1365
2023-03-20Implement Smrnmi extensionAndrew Waterman1-0/+7
We don't model any sources of RNMI, so this is mostly vestigial.
2023-01-27Enable Svadu control bits in menvcfg and henvcfgAaron Durbin1-1/+2
Add in the support for the HADE fields in menvcfg and henvcfg based off of the svadu ISA string. This only allows for the writable HADE bits being exposed when the svadu ISA string is employed. No other behavior is implemented.
2023-01-18Instantiate tdata/tinfo as const csrs when trigger_count == 0Jerry Zhao1-2/+0
2022-12-15Split decode.h into public decode.h and private decode_macros.hJerry Zhao1-0/+2
* decode.h contains constants/typedefs/classes. This should not depend on config.h * decode_macros.h contains internally used macros, and depends on config.h
2022-12-09refactor: add tdata3_csr_t; preparation for CSR textraYenHaoChen1-0/+8
2022-12-05refactor: add custom CSR class, mevent_csr_tYenHaoChen1-0/+7
The masked_csr_t does not meet the behavior of mevent because the misa.H is not read-only (hardwired). (fix in the next commit) h/t @kwalker27 reported at https://github.com/riscv-software-src/riscv-isa-sim/pull/1154
2022-11-22Add tinfo register.Tim Newsome1-0/+8
Not very interesting while spike only supports one trigger type, but #1128 is about to change that. Without tinfo, it can become quite slow for a debugger to discover which types are supported.
2022-11-17add support for zcmtWeiwei Li1-0/+6
add suport for jvt: Table entries follow the current data endianness
2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-10-04Fix remaining ignored-qualifiers warningAndrew Waterman1-1/+1
2022-09-20Merge pull request #1036 from plctlab/plct-sscofpmf-devAndrew Waterman1-0/+9
add support for sscofpmf extension v0.5.2
2022-08-11Unify PMPCFGx behaviour with PMPADDRx where PMP is disabled (#1068)Greg Chadwick1-0/+1
Previously any access to the PMPADDRx CSRs when no PMP regions were configured would result in an illegal instruction trap, whilst PMPCFGx registers would act as WARL, ignoring writes and reading as 0. This unifies the behaviour so both PMPADDRx and PMPCFGx CSRs produce an illegal instruction trap when accessed when no PMP regions are configured.
2022-08-09add support for sscofpmf extension v0.5.2Weiwei Li1-0/+9
since spike doesn't truly support counting of hardware performance events, only csr related read/write functions is supported currently
2022-08-08Merge pull request #1059 from plctlab/plct-stateen-fixAndrew Waterman1-6/+0
add stateen related check to frm/fflags
2022-08-03Add Sstc support. (#1057)i2h21-1/+16
2022-08-03add stateen related check to frm/fflags and then apply to fcsr implicitlyWeiwei Li1-6/+0
2022-07-21Merge pull request #1040 from plctlab/plct-priv-devAndrew Waterman1-7/+10
Update for counter related CSR
2022-07-21add support for time/timeh/htimedelta/htimedeltah csrsWeiwei Li1-0/+15
2022-07-21modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_tWeiwei Li1-14/+2
2022-07-18Merge pull request #1041 from plctlab/plct-new-csrsAndrew Waterman1-0/+1
add support for m/henvcfgh and mconfigptr CSRs
2022-07-17extract the progress of computing the inital value of mstatus intoWeiwei Li1-0/+1
separate function compute_mstatus_initial_value()
2022-07-15Merge pull request #1043 from YenHaoChen/pr-conditionalize-epmpAndrew Waterman1-0/+1
Conditionalize Smepmp extension (ePMP) support
2022-07-13Add proxy for accessing the low 32 bits of a 64-bit CSRScott Johnson1-0/+15
Use this for mstatus on RV32 so that `csrw mstatus` does not modify the bits in `mstatush`. Fixes #1044.
2022-07-13Remove no-longer-needed mask from rv32_high_csr_tScott Johnson1-1/+0
2022-07-13Remove unnecessary mask from rv32_high_csr_t constructorScott Johnson1-2/+2
2022-07-13Add verify_permissions() for mseccfg_csr_tYenHaoChen1-0/+1
The mseccfg only exists when enabling the Smepmp extension. If not enabling the Smepmp extension, CSR instructions to the mseccfg raise illegal instruction faults, and the PMP behaviors as hardwiring mseccfg 0 (the reset value of mseccfg).
2022-07-09add smstateen check for fcsr, senvcfg, henvcfgWeiwei Li1-0/+4
2022-07-09add standalone class for fcsr and senvcfg csrWeiwei Li1-0/+11
2022-07-09add support for csrs of smstateen extensionsWeiwei Li1-0/+19
2022-07-07modify mstatush_csr_t to general rv32_high_csr_tWeiwei Li1-4/+6
2022-07-07remove multi blank linesWeiwei Li1-37/+0
generated by cgit v1.1 at 2024-11-18 23:19:33 +0000