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2022-05-11Change henvcfg csr to a henvcfg_csr_tRyan Buchner1-0/+14
To do so implemented henvcfg_csr_t. henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0.
2022-05-04Implement the new csr mseccfg for ePMP as dummysoberl@nvidia.com1-0/+16
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson1-4/+1
Refactor trigger code
2022-04-04Refactor misa maskingMark Fedorov1-0/+1
2022-03-30Move tdata2 into mcontrol_tTim Newsome1-4/+1
2022-03-16Inline most implicit accesses to fflags/frmAndrew Waterman1-1/+3
2022-03-15Rewrite sstatus_csr_t::enabled() for higher performanceAndrew Waterman1-2/+5
Eliminate calls to base_status_csr_t::enabled() so that the various read() calls can be inlined. Doing so also removes a redundant check of sstatus_write_mask. Schedule the most common exit path first.
2022-03-15Give concrete types to fields of sstatus_proxy_csr_tAndrew Waterman1-2/+2
Doing so allows calls to their members to be inlined.
2022-03-15Give concrete types to fields of sstatus_csr_tAndrew Waterman1-3/+4
Doing so allows calls to their members to be inlined.
2022-03-15Allow sstatus_proxy_csr_t::read() to be inlinedAndrew Waterman1-2/+6
2022-03-15Allow mstatus_csr_t::read() to be inlinedAndrew Waterman1-2/+6
2022-03-15Allow vsstatus_csr_t::read() to be inlinedAndrew Waterman1-2/+6
2022-03-15Move sstatus_proxy_csr_t defn below that of mstatus_csr_tAndrew Waterman1-11/+11
This will allow the former to depend on the latter in a future commit.
2022-03-15Fix perf regression from CSR refactoring (#949)Andrew Waterman1-3/+13
Since many instructions are only conditionally legal, their implementations need to query misa (or isa). Since reading misa is therefore on the critical path, make sure it's inlined. Making misa_csr_t a final class sidesteps the need for a vtable lookup when calling read().
2022-02-18Split out MINSTRET and MCYCLERupert Swarbrick1-4/+4
Before this change, the MCYCLE CSR was just a proxy for MINSTRET. Similarly, CYCLE was a proxy for INSTRET. This models a machine where every instruction takes exactly one cycle to execute. That's not quite precise enough if you want to do cosimulation: there, you're going to want to MCYCLE to actually match the behaviour of your processor (because you need reads from the relevant CSRs to give the expected result). This commit splits the two CSRs, leaving the other proxy relationships unchanged. The code in processor_t::step() which bumps MINSTRET now bumps MCYCLE by the same amount, maintaining the previous behaviour. Of course, now a cosimulation environment can update the value of MCYCLE to fix things up for multi-cycle instructions after they run.
2022-02-18Rename minstret CSR classes to something more generalRupert Swarbrick1-7/+7
No other functional change. This is preparation for a follow-up commit, which will split MINSTRET and MCYCLE (to allow cosimulation environments where the two values might not be equal)
2021-11-13Use enum to specify the 3 options for masking of intr CSRsScott Johnson1-2/+3
Because using two booleans gives the impression that there are four possibilities. Since hideleg is itself masked by mideleg, there are effectively only three choices, so make that explicit via enum.
2021-11-13Mask hideleg by midelegScott Johnson1-0/+9
According to spec clarification: https://github.com/riscv/riscv-isa-manual/pull/771 This has no functional effect today, because all the active bits of hideleg are tied to 1 inside mideleg.
2021-11-02Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)Markku-Juhani O. Saarinen1-2/+2
Krypto 1.0 changes: Entropy source CSR, name. List scalar crypto instruction groupings, as there is no single K extension. Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
2021-10-15Fix clang warningAndrew Waterman1-1/+1
2021-10-06Make vxsat into its own classScott Johnson1-0/+8
Since its rules will need to be different than other vector CSRs (coming next). No functional change intended.
2021-10-06Let each sstatus CSR determine extension enableScott Johnson1-0/+2
No functional change intended. This will allow me to consider whether the given field exists at all, which I will eventually use to fix #823.
2021-10-06Give sstatus_csr_t handles to its base_status_csr_t constituentsScott Johnson1-1/+6
So I can add specialized methods to base_status_csr_t next, for use from within sstatus_csr_t.
2021-09-29Convert vlenb to csr_tScott Johnson1-1/+1
Since it's constant, no new trace events will be seen.
2021-09-29Convert vstart to csr_tScott Johnson1-0/+5
Adds commit log events for vstart to many vector instructions.
2021-09-29Convert vxsat to csr_tScott Johnson1-0/+11
Adds commit log events for vxsat to many vector instructions.
2021-09-28Convert sentropy to csr_tScott Johnson1-0/+11
2021-09-27Convert FCSR to csr_tScott Johnson1-0/+17
2021-09-27Convert frm & fflags to csr_tScott Johnson1-0/+9
Adds proper logging of fflags on FP arithmetic ops.
2021-09-27Merge pull request #815 from scottj97/mstatushAndrew Waterman1-0/+13
Convert mstatush to csr_t
2021-09-27Make mstatush bits writable on hypervisor configsScott Johnson1-0/+1
Fixes #812. Note that only GVA & MPV are actually writable; MBE and SBE are fixed inside mstatus_csr_t::unlogged_write().
2021-09-27Convert mstatush to csr_tScott Johnson1-0/+12
Maintains non-writability reported as issue #812
2021-09-26Convert dcsr to csr_tScott Johnson1-3/+11
2021-09-26Move dcsr_t definition to csrs.hScott Johnson1-0/+13
In prep for its conversion to csr_t.
2021-09-26Convert dpc to csr_tScott Johnson1-0/+6
2021-09-26Convert dscratch0/1 to csr_tScott Johnson1-0/+7
2021-09-26Convert tdata2 to csr_tScott Johnson1-0/+13
2021-09-26Convert tdata1 to csr_tScott Johnson1-0/+9
2021-09-26Convert tselect to csr_tScott Johnson1-0/+8
2021-09-25Remove no-longer-used counteren_csr_tScott Johnson1-9/+0
2021-09-25Convert hgatp to csr_tScott Johnson1-0/+10
2021-09-25Convert hstatus_csr_t to more generic masked_csr_tScott Johnson1-2/+5
Which I will reuse next for other CSRs.
2021-09-25Convert mtval2 to csr_tScott Johnson1-0/+8
2021-09-20Fix logged value of minstretScott Johnson1-0/+1
It was off by 1.
2021-09-20Provide mechanism (not yet used) for the logged value to be different from ↵Scott Johnson1-0/+4
read() I will need this soon for minstret.
2021-09-20Simplify logic and eliminate cpp macrosScott Johnson1-0/+2
2021-09-20Convert unprivileged counter shadows to csr_tScott Johnson1-0/+7
Soon I will simplify some of these cpp macros.
2021-09-16Convert mhpmcounter, mhpmevents to csr_tScott Johnson1-0/+12
2021-09-16Convert mcycle[h] (which is a mirror of minstret[h]) to csr_tScott Johnson1-0/+15
2021-09-16Convert minstreth to csr_tScott Johnson1-0/+12
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