riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2023-12-08	Remove cfg_arg_t from cfg_t	Jerry Zhao	1	-1/+1
	Argument parsing should be scoped to the code which constucts cfg_t
2023-12-08	Fix Spike --device option to pass on args to downstream plugins	joey0320	1	-1/+2

2023-06-20	device_t: Add device_factory_t's for ns16550/clint/plic	Jerry Zhao	1	-0/+31

2023-06-20	devices: Pass const pointers to sim_t to clint/plic	Jerry Zhao	1	-1/+1

2023-06-20	clint: Change clint_t::increment to override abstract_device_t::tick(rtc_ticks)	Jerry Zhao	1	-5/+5

2023-03-09	Use simif_t instead of sim_t for clint/plic	Scott Johnson	1	-2/+2
	In keeping with the spirit of simif_t.
2023-03-03	Fix misaligned accesses to clint's msip regs	Scott Johnson	1	-5/+7
	Misaligned MMIO is unspecified but this is simple enough.
2023-03-02	Initialize MTIP at reset	Scott Johnson	1	-0/+1
	Since mtime and mtimecmp both initialize to 0, and "a machine timer interrupt becomes pending whenever mtime contains a value greater than or equal to mtimecmp," MTIP should be 1. Before this change, MTIP would be 0 until the first increment, or until reading/writing from CLINT regs (since clint_t::load() and clint_t::store() call increment(0)).
2023-03-01	Support discontiguous hart IDs in CLINT	Andrew Waterman	1	-30/+47
	This is a large delta because the old implementation baked in multiple assumptions about the contiguity of hart IDs. As a side effect, fix implementation for big-endian hosts.
2022-12-20	Allow reads/writes to reserved CLINT regions	Jerry Zhao	1	-0/+4
	Previously, all loads/stores to reserved regions caused access faults. Now, loads to reserved regions return 0, while writes are dropped. This more closely matches actual hardware implementations
2022-07-21	add support for time/timeh/htimedelta/htimedeltah csrs	Weiwei Li	1	-0/+1

2021-09-08	Convert mip to csr_t family	Scott Johnson	1	-5/+5
	This changes the commitlog of `csrw sip` so that it only logs a change to `mip`, instead of both `mip` and `sip`. This is arguably preferable, since there is no real `sip` register -- it is only a view into `mip`. It also adds proper tracing of the modification to `mip` when doing `csrw` to `hip`, `hvip`, and `vsip`, which were all missing previously.
2020-02-15	Make CLINT API use Hz instead of MHz	Andrew Waterman	1	-3/+3

2020-02-15	Add optional support for real-time clint	Anup Patel	1	-3/+20
	This patch adds optional support clint timer incrementing at real-time rate. This can be enabled by passing command line parameter "--real-time-clint". This feature can be used for: 1. Checking whether any code addition to Spike is slowing down simulation too much 2. Comparing run-time for software on Spike with other functional simulators (such as QEMU) Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-11-27	Initialize mtime	Andrew Waterman	1	-1/+1
	Closes #363
2017-03-22	riscv: replace rtc device with a real clint implementation	Wesley W. Terpstra	1	-0/+72