Age | Commit message (Collapse) | Author | Files | Lines |
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Argument parsing should be scoped to the code which constucts cfg_t
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In keeping with the spirit of simif_t.
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Misaligned MMIO is unspecified but this is simple enough.
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Since mtime and mtimecmp both initialize to 0, and "a machine timer
interrupt becomes pending whenever mtime contains a value greater than
or equal to mtimecmp," MTIP should be 1.
Before this change, MTIP would be 0 until the first increment, or
until reading/writing from CLINT regs (since clint_t::load() and
clint_t::store() call increment(0)).
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This is a large delta because the old implementation baked in multiple
assumptions about the contiguity of hart IDs.
As a side effect, fix implementation for big-endian hosts.
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Previously, all loads/stores to reserved regions caused access faults.
Now, loads to reserved regions return 0, while writes are dropped.
This more closely matches actual hardware implementations
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This changes the commitlog of `csrw sip` so that it only logs a change
to `mip`, instead of both `mip` and `sip`. This is arguably
preferable, since there is no real `sip` register -- it is only a view
into `mip`.
It also adds proper tracing of the modification to `mip` when doing
`csrw` to `hip`, `hvip`, and `vsip`, which were all missing
previously.
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This patch adds optional support clint timer incrementing at
real-time rate. This can be enabled by passing command line
parameter "--real-time-clint".
This feature can be used for:
1. Checking whether any code addition to Spike is slowing down
simulation too much
2. Comparing run-time for software on Spike with other functional
simulators (such as QEMU)
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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Closes #363
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