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As proposed in #1652, we made the following changes to MMIO device (factory)
plugin API, to mitigate current limitations and facilitate factory reuse.
- removed `sargs` from `device_factory_t`, and introduced a new type alias
`device_factory_sargs_t` to capture `<device_factory_t *, sargs>` pairs,
this is used to instantiate sim_t instances;
- changed the signature of `device_factory_t::generate_fdt` and
`device_factory_t::parse_from_fdt` to take on an extra `sargs` argument,
for instantiating devices with per-device arguments;
- made `device_factory_t` const and potentially resuable across multiple
`sim_t` instances.
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riscv: sim.cc: Parse for "sifive,clint0" if "riscv,clint0" is absent
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"riscv,clint0" and "sifive,clint0" in device tree's "compatible" string point to the same driver,
as can be seen from drivers/clocksource/timer-clint.c in Linux kernel.
https://github.com/torvalds/linux/commit/2ac6795fcc085e8d03649f1bbd0d70aaff612cad
Signed-off-by: Tan En De <ende.tan@starfivetech.com>
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Argument parsing should be scoped to the code which constucts cfg_t
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In keeping with the spirit of simif_t.
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Misaligned MMIO is unspecified but this is simple enough.
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Since mtime and mtimecmp both initialize to 0, and "a machine timer
interrupt becomes pending whenever mtime contains a value greater than
or equal to mtimecmp," MTIP should be 1.
Before this change, MTIP would be 0 until the first increment, or
until reading/writing from CLINT regs (since clint_t::load() and
clint_t::store() call increment(0)).
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This is a large delta because the old implementation baked in multiple
assumptions about the contiguity of hart IDs.
As a side effect, fix implementation for big-endian hosts.
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Previously, all loads/stores to reserved regions caused access faults.
Now, loads to reserved regions return 0, while writes are dropped.
This more closely matches actual hardware implementations
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This changes the commitlog of `csrw sip` so that it only logs a change
to `mip`, instead of both `mip` and `sip`. This is arguably
preferable, since there is no real `sip` register -- it is only a view
into `mip`.
It also adds proper tracing of the modification to `mip` when doing
`csrw` to `hip`, `hvip`, and `vsip`, which were all missing
previously.
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This patch adds optional support clint timer incrementing at
real-time rate. This can be enabled by passing command line
parameter "--real-time-clint".
This feature can be used for:
1. Checking whether any code addition to Spike is slowing down
simulation too much
2. Comparing run-time for software on Spike with other functional
simulators (such as QEMU)
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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Closes #363
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