riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-24	fesvr: elfloader: replace asserts after open and mmap by exceptions	Viktor Prutyanov	1	-2/+4
2022-12-15	Add config.h includes directly to source files instead of relying on header c...	Jerry Zhao	1	-0/+1
2022-12-15	Rename memif_endianness_t to endianness_t	Jerry Zhao	1	-2/+2
2022-10-25	Remove set_target_endianness \| add --big-endian flag	Jerry Zhao	1	-2/+6
2022-09-20	detects the loading of isa-incompatible (i.e. 32 bit code to 64bit HART) code...	Iman Hosseini	1	-1/+5
2021-08-26	fesvr: replace use of `std::vector::operator[0]`	Saleem Abdulrasool	1	-1/+1
2021-08-26	fesvr: avoid an invalid memory access	Saleem Abdulrasool	1	-3/+5
2021-08-26	fesvr: format `LOAD_ELF` macro (NFC)	Saleem Abdulrasool	1	-43/+50
2020-11-26	Include stdexcept in ELF loader (#603)	Daniel Bates	1	-0/+1
2020-11-07	Implement support for big-endian targets	Marcus Comstedt	1	-5/+18
2020-01-25	Allow EM_NONE ELFs, too	Andrew Waterman	1	-1/+1
2020-01-25	Refuse to load non-EXEC/non-RISC-V/non-V1 ELFs (#388)	Alexander Lent	1	-0/+3
2019-10-28	Whithhold BE ELF loading until BE target support is available	Marcus Comstedt	1	-9/+3
2019-10-28	Implement support for big-endian hosts	Marcus Comstedt	1	-33/+41
2019-03-31	Add fesvr; only globally install fesvr headers/libsstatic-link	Andrew Waterman	1	-0/+89