| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2023-04-12 | Unify fesvr/debug_defines.h and riscv/debug_defines.h | Jerry Zhao | 1 | -60/+60 | |
| * fesvr/debug_defines.h is removed | |||||
| 2022-12-15 | Pull memif_endianness_t into cfg.h | Jerry Zhao | 1 | -3/+0 | |
| 2022-04-07 | Fix build of dtm.cc on RISC-V targets | Andrew Waterman | 1 | -1/+0 | |
| We don't actually need encoding.h, so don't include it. | |||||
| 2020-05-06 | Add missing stdexcept imports | Schuyler Eldridge | 1 | -0/+1 | |
| Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||||
| 2020-04-09 | op: update CSR | Chih-Min Chao | 1 | -2/+2 | |
| 1. add new hypervisor csr 2. add debug module csr 3. add some new high part register for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2020-03-29 | When enabling the debug module, poll til it's really enabled | Andrew Waterman | 1 | -0/+2 | |
| Resolves #435 | |||||
| 2020-02-11 | FESVR: ensure dmactive is 1 before reading debug module registers | Megan Wachs | 1 | -3/+3 | |
| 2020-02-10 | FESVR: Can't read a DM register when DMACTIVE=0 | Megan Wachs | 1 | -1/+1 | |
| 2019-03-31 | Add fesvr; only globally install fesvr headers/libsstatic-link | Andrew Waterman | 1 | -0/+642 | |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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