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PLIC: Implement threshold masking
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add hlvx pmp protect to fix issue 1557
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Support Zicfiss (shadow stack access) with CFI extension v0.4.0
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Make Zaamo + Zalrsc (Zba + Zbb + Zbs) imply A (B) in misa
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Assert misa.B bit through --isa=...B...
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1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
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Interaction: Support until-mem operation on physical memory space
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Ignore writes to henvcfg fields (PBMTE, STCE, and ADUE) when read-only 0
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The henvcfg fields, i.e., PBMTE, STCE, and ADUE, are read-only 0 when
the corresponding bits in menvcfg are 0. Besides the reading behavior,
the spec also specified the writing behavior, i.e., ignoring writes.
This commit ignores writes to the henvcfg fields when read-only 0.
Reference: https://github.com/riscv/riscv-isa-manual/issues/1312
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Narrow scontext.data length to 32
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The commit provdes the change between debug spec 1.0.0-rc1 and 1.0.0-rc2
Reference: https://github.com/riscv/riscv-debug-spec/pull/981
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Implement syscall readlinkat
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Allow software check exception to be delegated from M mode regardless of Zicfilp being enabled
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Zicfilp being enabled
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Support Zicfilp
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Update vcompress.vm to not write vstart with 0 upon completion
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Vmcompress.vm requires vstart==0, so writing vstart with 0 is redundant.
To do this, spin off VI_LOOP_END_BASE from VI_LOOP_END. VI_LOOP_END
will contain VI_LOOP_END_BASE as well as a write of 0 to vstart.
See #1623 for full discussion.
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workaround to support custom extensions that use standard prefixes
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RISC-V ISA states (21.1):
"A standard-compatible global encoding can also use standard prefixes
for non-standard extensions if the associated standard extensions are
not included in the global encoding."
Currently all the instructions (either from standard or custom
extensions) are all being inserted into a single std::vector which is
then being sorted. An instruction matching process performs linear
search on that vector. The problem is that when a custom extension uses
the same opcode as standard one (i.e. match and mask are equal to the
standard counterparts) it is undefined which instruction will be picked.
That is because in std::sort "The order of equal elements is not
guaranteed to be preserved". That being said it is impossible to define
custom extension (via customext) that would use the prefix of a disabled
standard extension.
In this change I separate custom and standard extensions in two separate
std::vector's. By default we report an error if they have common
elements (There're an additional processor_t constructor's argument that
skips this check). If this error is disabled during instruction matching
we first trying to find it among custom instructions. If it has been
found the search is stopped and custom instruction is executed,
otherwise we look for it among standard instructions. Overall this
change does not completely fix the problem but at least makes it
possible to use the feature of RISC-V ISA.
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Regenerates riscv/encoding.h and declares the new lpad insn as an overlapping
insn
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Bump GitHub Actions runners to Ubuntu 22.04
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Suppresses a warning on newer compilers for -std=c++20.
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Use -iquote instead. This prevents our include paths from messing up
the system headers depended upon by libstdc++. (The specific problem
was syscall.h in fesvr/, which was interfering with libstdc++'s
dependence on the system's syscall.h for SYS_futex.)
Subproject headers can now be included in the following ways:
#include "foo.h" // for a header local to this subproject
#include <bar/baz.h>" // for a header in another subproject
But no longer:
#include <baz.h> // for a header in any subproject
As a special case, libfdt needs itself to be added to the -I path,
because their coding style is to use angle brackets for local headers.
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Upgrade Spike to compile with c++2a and use designated initializers
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Fix help message to document `--device=<name>,<args>` usage by #1522
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Update README.md
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Fix c.mop.N decoding
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Add missing prerequisite libboost-regex-dev
Signed-off-by: Katharina <KatCe@users.noreply.github.com>
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Raise illegal instruction instead of virtual instruction on WFI when TW=1 and VTW=0 in VU-mode
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VU-mode
The previous implementation raises virtual instruction on WFI when TW=1 in VU-mode. According to the recent discussion, we expect an illegal instruction exception in this case.
Reference: https://github.com/riscv/riscv-isa-manual/issues/1234
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The c.mop.N only accepts rd={x1, x3, x5, x7, x9, x11, x13, x15}. The
previous implemention incorrectly accepts additional rd={x17, x19, x21,
x23, x25, x27, x29, x31}.
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Reduce NS16550 address space size to one page
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..rather than unbounded, as it used to be. This led to the rather
surprising issue #1600, where a part of the address space assumed to be
vacant would allow a subset of accesses.
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