| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2010-08-04 | [xcc,pk,sim] Added first part of FP support | Andrew Waterman | 20 | -22/+63 |
| 2010-08-03 | [sim,xcc] removed sll32/srl32/sra32 opcodes | Andrew Waterman | 4 | -24/+3 |
| 2010-08-03 | [pk,sim,xcc] Renamed instructions to RISC-V spec | Andrew Waterman | 56 | -97/+97 |
| 2010-07-28 | [gcc] generate code for complex branches | Andrew Waterman | 1 | -3/+0 |
| 2010-07-28 | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 83 | -668/+1223 |
| 2010-07-22 | [sim] various fixes to get the sim work with the fesvr | Yunsup Lee | 4 | -5/+11 |
| 2010-07-21 | [pk,sim] removed cop0 console i/o support | Andrew Waterman | 1 | -9/+0 |
| 2010-07-21 | [pk,sim] first cut of appserver communication link | Andrew Waterman | 12 | -27/+267 |
| 2010-07-19 | [pk,sim] added temporary "exit" functionality | Andrew Waterman | 1 | -0/+5 |
| 2010-07-18 | Reorganized directory structure | Andrew Waterman | 147 | -0/+11514 |
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index : riscv-isa-sim.git | |
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