Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2018-01-31 | Passes smoke tests with --progsize=0no_progbuf | Tim Newsome | 1 | -15/+82 | |
2018-01-30 | WIP. Doesn't work. | Tim Newsome | 2 | -40/+36 | |
2018-01-29 | Update debug_defines | Tim Newsome | 3 | -53/+53 | |
2018-01-18 | Support debug system bus access. | Tim Newsome | 5 | -20/+230 | |
2018-01-09 | Use new debug_defines.h. | Tim Newsome | 1 | -19/+19 | |
2018-01-08 | mem_t: Throw an error if zero-sized memory is requested (#168) | Jonathan Neuschäfer | 2 | -0/+4 | |
* mem_t: Throw an error if zero-sized memory is requested If for some reason the user requests a memory size of 0 megabytes, print a useful error message. * Check for overflow in memory size If the user passes in a large enough memory size (-m) that the size in bytes doesn't fit into size_t, catch this error in the make_mems function. | |||||
2018-01-03 | Add some missing RVC instructions to disassembler | Andrew Waterman | 1 | -0/+3 | |
2017-12-18 | Merge pull request #165 from riscv/small_progbuf | Tim Newsome | 7 | -484/+487 | |
Add support for program buffer of size 2 | |||||
2017-12-11 | Update debug_defines to latest version. | Tim Newsome | 1 | -22/+48 | |
2017-12-11 | Set impebreak. | Tim Newsome | 2 | -1/+9 | |
2017-12-11 | Update to latest debug_defines.h. | Tim Newsome | 3 | -465/+411 | |
2017-12-11 | Make progbuf a run-time option. | Tim Newsome | 6 | -19/+42 | |
Also add an implicit ebreak after the program buffer. This is not part of the spec, but hopefully it will be. | |||||
2017-11-27 | Rename badaddr to tval | Andrew Waterman | 5 | -25/+25 | |
2017-11-27 | Rename sptbr to satp | Andrew Waterman | 5 | -36/+36 | |
2017-11-27 | Set tval to 0 on traps with no specified tval | Andrew Waterman | 2 | -5/+3 | |
Simply not writing the register was not a conformant implementation. | |||||
2017-11-20 | Implement priv-1.11 interrupt-priority scheme (#161) | Andrew Waterman | 1 | -1/+18 | |
Closes #159. https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3 | |||||
2017-11-20 | Fix commitlog. (#162) | Christopher Celio | 1 | -5/+8 | |
A regression caused any instruction with rd=x0 to not be emitted. | |||||
2017-11-15 | Merge pull request #156 from p12nGH/noncontiguous_harts | Andrew Waterman | 3 | -5/+31 | |
Support for non-contiguous hartids | |||||
2017-11-15 | hartids knob description added | Gleb Gagarin | 1 | -0/+1 | |
2017-11-15 | Support for non-contiguous hartids | Gleb Gagarin | 3 | -5/+30 | |
2017-11-09 | Remove redundant U/S mode advertisement | Andrew Waterman | 1 | -4/+0 | |
2017-11-09 | H-mode no longer exists | Andrew Waterman | 2 | -2/+0 | |
It's supplanted by the hypervisor extension, which doesn't use the privilege encoding of 2; it still looks like supervisor (i.e. 1). | |||||
2017-11-09 | MPP is now WARL | Andrew Waterman | 2 | -6/+23 | |
2017-11-06 | Implement Q extension for disassembler (#153) | Kito Cheng | 1 | -0/+36 | |
2017-11-03 | Fix disassembly of c.li 0 | Andrew Waterman | 1 | -1/+1 | |
Resolves #152 | |||||
2017-11-03 | Merge pull request #151 from riscv/htif_dts | Palmer Dabbelt | 1 | -0/+3 | |
Put HTIF in the device tree | |||||
2017-11-03 | Put HTIF in the device tree | Palmer Dabbelt | 1 | -0/+3 | |
I wanted to actually put the address of the HTIF into the DTS, but that seems to be a bit too much work: since the HTIF addresses are just defined in an ELF file it's a bit awkward to make that work. Instead, I'm just putting a dummy HTIF key in the DTS. | |||||
2017-11-02 | Mask medeleg correctly | Andrew Waterman | 1 | -3/+7 | |
2017-11-01 | Don't permit delegation of interrupts that M-mode should handle | Andrew Waterman | 1 | -4/+3 | |
2017-10-20 | Fix commit-log for Q extension, and for RV32 (#143) | Andrew Waterman | 3 | -18/+53 | |
* Fix commit-log for Q extension, and for RV32 The number of nibbles printed out now depends upon XLEN or FLEN, as appropriate. * Factor out FLEN calculation | |||||
2017-10-19 | Fix bus_t bug with devices at 0x0 | Evan Cox | 1 | -10/+30 | |
Fix a bug that prevented bus_t from storing to, loading from, or finding a device that existed at address 0x0. Resolves: #135 | |||||
2017-10-19 | Fix implementation of FMIN/FMAX NaN case | Andrew Waterman | 6 | -6/+12 | |
If rd=rs1 or rd=rs2, the NaN check examined the wrong value. | |||||
2017-10-15 | Include math.h for NAN (#137) | jar | 1 | -0/+1 | |
commit 85c40db208db3e26f507dc6a74a5dc540b504b5c introduced a NAN dependency but did not include the math.h header | |||||
2017-10-10 | Merge pull request #129 from riscv/q-extension | Andrew Waterman | 263 | -1092/+11453 | |
Implement Q extension | |||||
2017-09-28 | Implement Q extension | Andrew Waterman | 45 | -24/+258 | |
2017-09-25 | Merge pull request #128 from riscv/reset | Tim Newsome | 1 | -1/+8 | |
Fix debug reset. | |||||
2017-09-24 | Update SoftFloat | Andrew Waterman | 218 | -1068/+11195 | |
2017-09-21 | Actually let hartreset be set. | Tim Newsome | 1 | -0/+1 | |
2017-09-21 | Fix debug reset. | Tim Newsome | 1 | -1/+7 | |
ndmreset now resets all harts (instead of just the current hart), and hartreset resets the selected hart (instead of being ignored). | |||||
2017-09-21 | Fix corner case in repeated execution (#127) | Tim Newsome | 2 | -4/+4 | |
Specifically, don't print out the execution count if the same instruction is executed by different harts. | |||||
2017-09-21 | Fix comment typo. (#126) | Tim Newsome | 1 | -1/+1 | |
2017-09-12 | Merge pull request #123 from riscv/debug_interrupts | Tim Newsome | 1 | -1/+1 | |
Don't take interrupts while in Debug Mode. | |||||
2017-09-12 | Don't take interrupts while in Debug Mode. | Tim Newsome | 1 | -1/+1 | |
2017-08-28 | Merge pull request #121 from riscv/debug_store | Tim Newsome | 1 | -1/+13 | |
Add a nice debug printf for debug_module_t::store | |||||
2017-08-28 | Add a nice debug printf for debug_module_t::store | Tim Newsome | 1 | -1/+13 | |
2017-08-11 | Merge pull request #119 from riscv/quiet | Tim Newsome | 1 | -2/+2 | |
Turn off debug module debug printfs. | |||||
2017-08-11 | Turn off debug module debug printfs. | Tim Newsome | 1 | -2/+2 | |
Nobody wants to see all that, and if they do they should recompile. | |||||
2017-08-10 | Correct c.li and c.lui disassembly (#118) | Palmer Dabbelt | 1 | -2/+2 | |
I currently get this disassembly 00004881 jr a7 but if I understand that's incorrect and I want 00004881 li a7, 0 If I'm reading the ISA manual correctly, the disassembler was just wrong here. | |||||
2017-08-10 | Merge pull request #117 from riscv/multicore_debug | Tim Newsome | 3 | -18/+12 | |
Fix multicore debug. | |||||
2017-08-07 | Fix multicore debug. | Tim Newsome | 3 | -18/+12 | |
In an older implementation I was thinking of having different entry points for different harts, but that's no longer true. Also get rid of a bunch of trailing whitespace. |