diff options
| -rw-r--r-- | disasm/disasm.cc | 61 | ||||
| -rw-r--r-- | disasm/isa_parser.cc | 2 | ||||
| -rw-r--r-- | riscv/encoding.h | 46 | ||||
| -rw-r--r-- | riscv/insns/mop_r_N.h | 2 | ||||
| -rw-r--r-- | riscv/insns/mop_rr_N.h | 2 | ||||
| -rw-r--r-- | riscv/isa_parser.h | 1 | ||||
| -rw-r--r-- | riscv/riscv.mk.in | 5 |
7 files changed, 109 insertions, 10 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index ad48ea8..08571a2 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2172,15 +2172,58 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DEFINE_RTYPE(czero_nez); } + if (isa->extension_enabled(EXT_ZIMOP)) { + DEFINE_R1TYPE(mop_r_0); + DEFINE_R1TYPE(mop_r_1); + DEFINE_R1TYPE(mop_r_2); + DEFINE_R1TYPE(mop_r_3); + DEFINE_R1TYPE(mop_r_4); + DEFINE_R1TYPE(mop_r_5); + DEFINE_R1TYPE(mop_r_6); + DEFINE_R1TYPE(mop_r_7); + DEFINE_R1TYPE(mop_r_8); + DEFINE_R1TYPE(mop_r_9); + DEFINE_R1TYPE(mop_r_10); + DEFINE_R1TYPE(mop_r_11); + DEFINE_R1TYPE(mop_r_12); + DEFINE_R1TYPE(mop_r_13); + DEFINE_R1TYPE(mop_r_14); + DEFINE_R1TYPE(mop_r_15); + DEFINE_R1TYPE(mop_r_16); + DEFINE_R1TYPE(mop_r_17); + DEFINE_R1TYPE(mop_r_18); + DEFINE_R1TYPE(mop_r_19); + DEFINE_R1TYPE(mop_r_20); + DEFINE_R1TYPE(mop_r_21); + DEFINE_R1TYPE(mop_r_22); + DEFINE_R1TYPE(mop_r_23); + DEFINE_R1TYPE(mop_r_24); + DEFINE_R1TYPE(mop_r_25); + DEFINE_R1TYPE(mop_r_26); + DEFINE_R1TYPE(mop_r_27); + DEFINE_R1TYPE(mop_r_28); + DEFINE_R1TYPE(mop_r_29); + DEFINE_R1TYPE(mop_r_30); + DEFINE_R1TYPE(mop_r_31); + DEFINE_RTYPE(mop_rr_0); + DEFINE_RTYPE(mop_rr_1); + DEFINE_RTYPE(mop_rr_2); + DEFINE_RTYPE(mop_rr_3); + DEFINE_RTYPE(mop_rr_4); + DEFINE_RTYPE(mop_rr_5); + DEFINE_RTYPE(mop_rr_6); + DEFINE_RTYPE(mop_rr_7); + } + if (isa->extension_enabled(EXT_ZCMOP)) { - DISASM_INSN("c.mop.1", c_mop_1, 0, {}); - DISASM_INSN("c.mop.3", c_mop_3, 0, {}); - DISASM_INSN("c.mop.5", c_mop_5, 0, {}); - DISASM_INSN("c.mop.7", c_mop_7, 0, {}); - DISASM_INSN("c.mop.9", c_mop_9, 0, {}); - DISASM_INSN("c.mop.11", c_mop_11, 0, {}); - DISASM_INSN("c.mop.13", c_mop_13, 0, {}); - DISASM_INSN("c.mop.15", c_mop_15, 0, {}); + DISASM_INSN("c.mop.1", c_mop_1, 0, {}); + DISASM_INSN("c.mop.3", c_mop_3, 0, {}); + DISASM_INSN("c.mop.5", c_mop_5, 0, {}); + DISASM_INSN("c.mop.7", c_mop_7, 0, {}); + DISASM_INSN("c.mop.9", c_mop_9, 0, {}); + DISASM_INSN("c.mop.11", c_mop_11, 0, {}); + DISASM_INSN("c.mop.13", c_mop_13, 0, {}); + DISASM_INSN("c.mop.15", c_mop_15, 0, {}); } if (isa->extension_enabled(EXT_ZKND) || @@ -2347,7 +2390,7 @@ disassembler_t::disassembler_t(const isa_parser_t *isa) // next-highest priority: other instructions in same base ISA std::string fallback_isa_string = std::string("rv") + std::to_string(isa->get_max_xlen()) + - "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zicond_zkn_zkr_zks_svinval_zcmop"; + "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zicond_zkn_zkr_zks_svinval_zcmop_zimop"; isa_parser_t fallback_isa(fallback_isa_string.c_str(), DEFAULT_PRIV); add_instructions(&fallback_isa); diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index ef51310..fa8cadd 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -294,6 +294,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) extension_table[EXT_SSCSRIND] = true; } else if (ext_str == "smcntrpmf") { extension_table[EXT_SMCNTRPMF] = true; + } else if (ext_str == "zimop") { + extension_table[EXT_ZIMOP] = true; } else if (ext_str == "zcmop") { extension_table[EXT_ZCMOP] = true; } else if (ext_str == "zalasr") { diff --git a/riscv/encoding.h b/riscv/encoding.h index 81d829c..78318a6 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -4,7 +4,7 @@ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (37413c8) + * https://github.com/riscv/riscv-opcodes (61d2ef4) */ #ifndef RISCV_CSR_ENCODING_H @@ -29,6 +29,7 @@ #define MSTATUS_TVM 0x00100000 #define MSTATUS_TW 0x00200000 #define MSTATUS_TSR 0x00400000 +#define MSTATUS_SPELP 0x00800000 #define MSTATUS32_SD 0x80000000 #define MSTATUS_UXL 0x0000000300000000 #define MSTATUS_SXL 0x0000000C00000000 @@ -36,6 +37,7 @@ #define MSTATUS_MBE 0x0000002000000000 #define MSTATUS_GVA 0x0000004000000000 #define MSTATUS_MPV 0x0000008000000000 +#define MSTATUS_MPELP 0x0000020000000000 #define MSTATUS64_SD 0x8000000000000000 #define MSTATUSH_SBE 0x00000010 @@ -54,6 +56,7 @@ #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 #define SSTATUS_MXR 0x00080000 +#define SSTATUS_SPELP 0x00800000 #define SSTATUS32_SD 0x80000000 #define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 @@ -79,6 +82,7 @@ #define DCSR_XDEBUGVER (3U<<30) #define DCSR_NDRESET (1<<29) #define DCSR_FULLRESET (1<<28) +#define DCSR_PELP (1<<18) #define DCSR_EBREAKM (1<<15) #define DCSR_EBREAKH (1<<14) #define DCSR_EBREAKS (1<<13) @@ -157,6 +161,8 @@ #define SIP_STIP MIP_STIP #define MENVCFG_FIOM 0x00000001 +#define MENVCFG_LPE 0x00000004 +#define MENVCFG_SSE 0x00000008 #define MENVCFG_CBIE 0x00000030 #define MENVCFG_CBCFE 0x00000040 #define MENVCFG_CBZE 0x00000080 @@ -195,6 +201,8 @@ #define MHPMEVENTH_OF 0x80000000 #define HENVCFG_FIOM 0x00000001 +#define HENVCFG_LPE 0x00000004 +#define HENVCFG_SSE 0x00000008 #define HENVCFG_CBIE 0x00000030 #define HENVCFG_CBCFE 0x00000040 #define HENVCFG_CBZE 0x00000080 @@ -230,6 +238,8 @@ #define HSTATEENH_SSTATEEN 0x80000000 #define SENVCFG_FIOM 0x00000001 +#define SENVCFG_LPE 0x00000004 +#define SENVCFG_SSE 0x00000008 #define SENVCFG_CBIE 0x00000030 #define SENVCFG_CBCFE 0x00000040 #define SENVCFG_CBZE 0x00000080 @@ -243,6 +253,7 @@ #define MSECCFG_RLB 0x00000004 #define MSECCFG_USEED 0x00000100 #define MSECCFG_SSEED 0x00000200 +#define MSECCFG_MLPE 0x00000400 /* jvt fields */ #define JVT_MODE 0x3F @@ -682,6 +693,10 @@ #define MASK_C_SRAI 0xec03 #define MATCH_C_SRLI 0x8001 #define MASK_C_SRLI 0xec03 +#define MATCH_C_SSPOPCHK_X5 0x6281 +#define MASK_C_SSPOPCHK_X5 0xffff +#define MATCH_C_SSPUSH_X1 0x6081 +#define MASK_C_SSPUSH_X1 0xffff #define MATCH_C_SUB 0x8c01 #define MASK_C_SUB 0xfc63 #define MATCH_C_SUBW 0x9c01 @@ -1990,6 +2005,20 @@ #define MASK_SROIW 0xfe00707f #define MATCH_SROW 0x2000503b #define MASK_SROW 0xfe00707f +#define MATCH_SSAMOSWAP_D 0x4800302f +#define MASK_SSAMOSWAP_D 0xf800707f +#define MATCH_SSAMOSWAP_W 0x4800202f +#define MASK_SSAMOSWAP_W 0xf800707f +#define MATCH_SSPOPCHK_X1 0xcdc0c073 +#define MASK_SSPOPCHK_X1 0xffffffff +#define MATCH_SSPOPCHK_X5 0xcdc2c073 +#define MASK_SSPOPCHK_X5 0xffffffff +#define MATCH_SSPUSH_X1 0xce104073 +#define MASK_SSPUSH_X1 0xffffffff +#define MATCH_SSPUSH_X5 0xce504073 +#define MASK_SSPUSH_X5 0xffffffff +#define MATCH_SSRDP 0xcdc04073 +#define MASK_SSRDP 0xfffff07f #define MATCH_STAS16 0xf4002077 #define MASK_STAS16 0xfe00707f #define MATCH_STAS32 0xf0002077 @@ -3102,6 +3131,7 @@ #define CSR_VXSAT 0x9 #define CSR_VXRM 0xa #define CSR_VCSR 0xf +#define CSR_SSP 0x11 #define CSR_SEED 0x15 #define CSR_JVT 0x17 #define CSR_CYCLE 0xc00 @@ -3560,6 +3590,8 @@ #define CAUSE_FETCH_PAGE_FAULT 0xc #define CAUSE_LOAD_PAGE_FAULT 0xd #define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_SOFTWARE_CHECK_FAULT 0x12 +#define CAUSE_HARDWARE_ERROR_FAULT 0x13 #define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 #define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 #define CAUSE_VIRTUAL_INSTRUCTION 0x16 @@ -3823,6 +3855,8 @@ DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ) DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP) DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_sspopchk_x5, MATCH_C_SSPOPCHK_X5, MASK_C_SSPOPCHK_X5) +DECLARE_INSN(c_sspush_x1, MATCH_C_SSPUSH_X1, MASK_C_SSPUSH_X1) DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) @@ -4477,6 +4511,13 @@ DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) +DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D) +DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W) +DECLARE_INSN(sspopchk_x1, MATCH_SSPOPCHK_X1, MASK_SSPOPCHK_X1) +DECLARE_INSN(sspopchk_x5, MATCH_SSPOPCHK_X5, MASK_SSPOPCHK_X5) +DECLARE_INSN(sspush_x1, MATCH_SSPUSH_X1, MASK_SSPUSH_X1) +DECLARE_INSN(sspush_x5, MATCH_SSPUSH_X5, MASK_SSPUSH_X5) +DECLARE_INSN(ssrdp, MATCH_SSRDP, MASK_SSRDP) DECLARE_INSN(stas16, MATCH_STAS16, MASK_STAS16) DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32) DECLARE_INSN(stsa16, MATCH_STSA16, MASK_STSA16) @@ -5038,6 +5079,7 @@ DECLARE_CSR(vstart, CSR_VSTART) DECLARE_CSR(vxsat, CSR_VXSAT) DECLARE_CSR(vxrm, CSR_VXRM) DECLARE_CSR(vcsr, CSR_VCSR) +DECLARE_CSR(ssp, CSR_SSP) DECLARE_CSR(seed, CSR_SEED) DECLARE_CSR(jvt, CSR_JVT) DECLARE_CSR(cycle, CSR_CYCLE) @@ -5497,6 +5539,8 @@ DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +DECLARE_CAUSE("software check fault", CAUSE_SOFTWARE_CHECK_FAULT) +DECLARE_CAUSE("hardware error fault", CAUSE_HARDWARE_ERROR_FAULT) DECLARE_CAUSE("fetch guest page fault", CAUSE_FETCH_GUEST_PAGE_FAULT) DECLARE_CAUSE("load guest page fault", CAUSE_LOAD_GUEST_PAGE_FAULT) DECLARE_CAUSE("virtual instruction", CAUSE_VIRTUAL_INSTRUCTION) diff --git a/riscv/insns/mop_r_N.h b/riscv/insns/mop_r_N.h new file mode 100644 index 0000000..fa2687e --- /dev/null +++ b/riscv/insns/mop_r_N.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZIMOP); +WRITE_RD(0); diff --git a/riscv/insns/mop_rr_N.h b/riscv/insns/mop_rr_N.h new file mode 100644 index 0000000..fa2687e --- /dev/null +++ b/riscv/insns/mop_rr_N.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZIMOP); +WRITE_RD(0); diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index a84b6fe..7773ba5 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -81,6 +81,7 @@ typedef enum { EXT_SMCSRIND, EXT_SSCSRIND, EXT_SMCNTRPMF, + EXT_ZIMOP, EXT_ZCMOP, EXT_ZALASR, NUM_ISA_EXTENSIONS diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 76c2ed7..04747c9 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1388,6 +1388,10 @@ riscv_insn_ext_zvksh = \ vsm3c_vi \ vsm3me_vv \ +riscv_insn_ext_zimop = \ + mop_r_N \ + mop_rr_N \ + riscv_insn_ext_zvk = \ $(riscv_insn_ext_zvbb) \ $(riscv_insn_ext_zvbc) \ @@ -1426,6 +1430,7 @@ riscv_insn_list = \ $(riscv_insn_priv) \ $(riscv_insn_smrnmi) \ $(riscv_insn_svinval) \ + $(riscv_insn_ext_zimop) \ riscv_gen_srcs = $(addsuffix .cc,$(riscv_insn_list)) |