diff options
| -rw-r--r-- | riscv/sim.h | 5 | ||||
| -rw-r--r-- | riscv/simif.h | 9 |
2 files changed, 11 insertions, 3 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 909d71a..33995d3 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -52,10 +52,9 @@ public: } const char* get_dts() { return dts.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } - const cfg_t &get_cfg() { return *cfg; } - unsigned nprocs() const { return procs.size(); } + virtual const cfg_t &get_cfg() const override { return *cfg; } - const std::map<size_t, processor_t*>& get_harts() { return harts; } + virtual const std::map<size_t, processor_t*>& get_harts() const override { return harts; } // Callback for processors to let the simulation know they were reset. virtual void proc_reset(unsigned id) override; diff --git a/riscv/simif.h b/riscv/simif.h index c756b9c..74ddcdf 100644 --- a/riscv/simif.h +++ b/riscv/simif.h @@ -3,7 +3,11 @@ #ifndef _RISCV_SIMIF_H #define _RISCV_SIMIF_H +#include <map> #include "decode.h" +#include "cfg.h" + +class processor_t; // this is the interface to the simulator used by the processors and memory class simif_t @@ -19,10 +23,15 @@ public: // Callback for processors to let the simulation know they were reset. virtual void proc_reset(unsigned id) = 0; + virtual const cfg_t &get_cfg() const = 0; + virtual const std::map<size_t, processor_t*>& get_harts() const = 0; + virtual const char* get_symbol(uint64_t paddr) = 0; virtual ~simif_t() = default; + unsigned nprocs() const { return get_cfg().nprocs(); } + }; #endif |