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| author | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2022-11-14 16:53:17 +0300 |
|---|---|---|
| committer | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2022-11-15 13:05:45 +0300 |
| commit | 4470418b809ab4a439c468b0714bd15cde3cde46 (patch) | |
| tree | d0699c1316ebd12785a2d572ee47b69fdb125b5f /spike_main | |
| parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
| download | riscv-isa-sim-4470418b809ab4a439c468b0714bd15cde3cde46.zip riscv-isa-sim-4470418b809ab4a439c468b0714bd15cde3cde46.tar.gz riscv-isa-sim-4470418b809ab4a439c468b0714bd15cde3cde46.tar.bz2 | |
get rid of redundant casts during mem layout processing
Diffstat (limited to 'spike_main')
| -rw-r--r-- | spike_main/spike.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 933f626..2df3223 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -176,16 +176,15 @@ static std::vector<mem_cfg_t> parse_mem_layout(const char* arg) size += PGSIZE - size % PGSIZE; if (size != size0) { - fprintf(stderr, "Warning: the memory at [0x%llX, 0x%llX] has been realigned\n" + fprintf(stderr, "Warning: the memory at [0x%llX, 0x%llX] has been realigned\n" "to the %ld KiB page size: [0x%llX, 0x%llX]\n", base0, base0 + size0 - 1, long(PGSIZE / 1024), base, base + size - 1); } if (!mem_cfg_t::check_if_supported(base, size)) { - fprintf(stderr, "unsupported memory region " + fprintf(stderr, "Unsupported memory region " "{base = 0x%llX, size = 0x%llX} specified\n", - (unsigned long long)base, - (unsigned long long)size); + base, size); exit(EXIT_FAILURE); } |