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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-24 18:09:26 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-24 18:10:00 -0700 |
| commit | e78da5da4a6e6a38953cda9b35992c421768c776 (patch) | |
| tree | 9191d1770f2cef9e0b748537ac3a612899f56133 /riscv/sim.cc | |
| parent | 3258ff6431d22da76bd1cd873789a6c82d0af3b0 (diff) | |
| download | riscv-isa-sim-e78da5da4a6e6a38953cda9b35992c421768c776.zip riscv-isa-sim-e78da5da4a6e6a38953cda9b35992c421768c776.tar.gz riscv-isa-sim-e78da5da4a6e6a38953cda9b35992c421768c776.tar.bz2 | |
Refactor memory access code; add MMIO support
Of course, it doesn't do anything yet.
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 66bebb3..f7ff11d 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -144,3 +144,12 @@ void sim_t::set_procs_debug(bool value) procs[i]->set_debug(value); } +bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) +{ + return false; +} + +bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) +{ + return false; +} |