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author | Elmar Melcher <elmar@dsc.ufcg.edu.br> | 2021-07-02 11:03:27 -0300 |
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committer | emelcher <elmar@dsc.ufcg.edu.br> | 2021-08-03 10:19:27 -0300 |
commit | e30c9c90efa415a493ba2984a777bf53d1b8cbca (patch) | |
tree | 4c74267beaa9686e6d8ddadc0252c8372584184b /riscv/sim.cc | |
parent | e767bde210940b0a92e0f4c034c872759005ba5b (diff) | |
download | riscv-isa-sim-e30c9c90efa415a493ba2984a777bf53d1b8cbca.zip riscv-isa-sim-e30c9c90efa415a493ba2984a777bf53d1b8cbca.tar.gz riscv-isa-sim-e30c9c90efa415a493ba2984a777bf53d1b8cbca.tar.bz2 |
declare socket properties in sim_t
Diffstat (limited to 'riscv/sim.cc')
-rw-r--r-- | riscv/sim.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 1418af4..7b1e669 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -36,7 +36,11 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, std::vector<int> const hartids, const debug_module_config_t &dm_config, const char *log_path, - bool dtb_enabled, const char *dtb_file) + bool dtb_enabled, const char *dtb_file +#ifdef HAVE_BOOST_ASIO + , io_service *io_service_ptr_ctor, tcp::acceptor *acceptor_ptr_ctor // option -s +#endif + ) : htif_t(args), mems(mems), plugin_devices(plugin_devices), @@ -48,6 +52,7 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, dtb_file(dtb_file ? dtb_file : ""), dtb_enabled(dtb_enabled), log_file(log_path), + sout(nullptr), current_step(0), current_proc(0), debug(false), @@ -57,6 +62,7 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, debug_module(this, dm_config) { signal(SIGINT, &handle_signal); + sout.rdbuf(cerr.rdbuf()); // debug output goes to stderr by default for (auto& x : mems) bus.add_device(x.first, x.second); |