diff options
| author | Andrew Waterman <andrew@sifive.com> | 2020-03-29 18:11:49 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-29 18:11:49 -0700 |
| commit | a346ad57a2144f3af0759605c9268711c8bd670b (patch) | |
| tree | 0f98659a89113f4a701c2cb604fa6cb97c4e0f0b /riscv/sim.cc | |
| parent | 1ff8764fa0df9ed164149bbb59d7f4d05fcf70f8 (diff) | |
| download | riscv-isa-sim-a346ad57a2144f3af0759605c9268711c8bd670b.zip riscv-isa-sim-a346ad57a2144f3af0759605c9268711c8bd670b.tar.gz riscv-isa-sim-a346ad57a2144f3af0759605c9268711c8bd670b.tar.bz2 | |
Fix debug segfault by partially reverting #409
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 3a0ad73..0b29720 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -35,6 +35,7 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, const debug_module_config_t &dm_config, const char *log_path) : htif_t(args), mems(mems), plugin_devices(plugin_devices), + procs(std::max(nprocs, size_t(1))), initrd_start(initrd_start), initrd_end(initrd_end), start_pc(start_pc), log_file(log_path), current_step(0), current_proc(0), debug(false), histogram_enabled(false), @@ -63,8 +64,8 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, for (size_t i = 0; i < nprocs; i++) { int hart_id = hartids.empty() ? i : hartids[i]; - procs.push_back(new processor_t (isa, priv, varch, this, - hart_id, halted, log_file.get())); + procs[i] = new processor_t(isa, priv, varch, this, hart_id, halted, + log_file.get()); } clint.reset(new clint_t(procs, CPU_HZ / INSNS_PER_RTC_TICK, real_time_clint)); |