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| author | Tim Newsome <tim@sifive.com> | 2016-05-06 12:14:22 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:12 -0700 |
| commit | 9b8b9b69d0b2560b2727330d5a20b5133af140af (patch) | |
| tree | 1225b5caae6af4e4874ea9a516f2684e87d7db40 /riscv/sim.cc | |
| parent | 7e5c1b420d0b332d6663a47182f9a472e400f663 (diff) | |
| download | riscv-isa-sim-9b8b9b69d0b2560b2727330d5a20b5133af140af.zip riscv-isa-sim-9b8b9b69d0b2560b2727330d5a20b5133af140af.tar.gz riscv-isa-sim-9b8b9b69d0b2560b2727330d5a20b5133af140af.tar.bz2 | |
Make -H halt the core right out of reset.
Added a test, too.
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 4b4eed4..d17289d 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -47,9 +47,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, debug_mmu = new mmu_t(this, NULL); for (size_t i = 0; i < procs.size(); i++) { - procs[i] = new processor_t(isa, this, i); - if (halted) - procs[i]->enter_debug_mode(DCSR_CAUSE_HALT); + procs[i] = new processor_t(isa, this, i, halted); } rtc.reset(new rtc_t(procs)); |